266 lines
6.4 KiB
C
266 lines
6.4 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2013-2021 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_iosf_mbi.h"
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#include "vlv_sideband.h"
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/*
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* IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
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* VLV_VLV2_PUNIT_HAS_0.8.docx
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*/
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/* Standard MMIO read, non-posted */
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#define SB_MRD_NP 0x00
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/* Standard MMIO write, non-posted */
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#define SB_MWR_NP 0x01
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/* Private register read, double-word addressing, non-posted */
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#define SB_CRRDDA_NP 0x06
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/* Private register write, double-word addressing, non-posted */
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#define SB_CRWRDA_NP 0x07
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static void ping(void *info)
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{
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}
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static void __vlv_punit_get(struct drm_i915_private *i915)
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{
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iosf_mbi_punit_acquire();
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/*
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* Prevent the cpu from sleeping while we use this sideband, otherwise
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* the punit may cause a machine hang. The issue appears to be isolated
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* with changing the power state of the CPU package while changing
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* the power state via the punit, and we have only observed it
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* reliably on 4-core Baytail systems suggesting the issue is in the
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* power delivery mechanism and likely to be board/function
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* specific. Hence we presume the workaround needs only be applied
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* to the Valleyview P-unit and not all sideband communications.
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*/
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if (IS_VALLEYVIEW(i915)) {
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cpu_latency_qos_update_request(&i915->sb_qos, 0);
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on_each_cpu(ping, NULL, 1);
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}
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}
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static void __vlv_punit_put(struct drm_i915_private *i915)
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{
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if (IS_VALLEYVIEW(i915))
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cpu_latency_qos_update_request(&i915->sb_qos,
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PM_QOS_DEFAULT_VALUE);
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iosf_mbi_punit_release();
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}
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void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)
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{
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if (ports & BIT(VLV_IOSF_SB_PUNIT))
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__vlv_punit_get(i915);
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mutex_lock(&i915->sb_lock);
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}
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void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
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{
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mutex_unlock(&i915->sb_lock);
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if (ports & BIT(VLV_IOSF_SB_PUNIT))
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__vlv_punit_put(i915);
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}
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static int vlv_sideband_rw(struct drm_i915_private *i915,
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u32 devfn, u32 port, u32 opcode,
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u32 addr, u32 *val)
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{
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struct intel_uncore *uncore = &i915->uncore;
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const bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
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int err;
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lockdep_assert_held(&i915->sb_lock);
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if (port == IOSF_PORT_PUNIT)
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iosf_mbi_assert_punit_acquired();
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/* Flush the previous comms, just in case it failed last time. */
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if (intel_wait_for_register(uncore,
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VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
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5)) {
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drm_dbg(&i915->drm, "IOSF sideband idle wait (%s) timed out\n",
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is_read ? "read" : "write");
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return -EAGAIN;
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}
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preempt_disable();
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intel_uncore_write_fw(uncore, VLV_IOSF_ADDR, addr);
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intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
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intel_uncore_write_fw(uncore, VLV_IOSF_DOORBELL_REQ,
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(devfn << IOSF_DEVFN_SHIFT) |
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(opcode << IOSF_OPCODE_SHIFT) |
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(port << IOSF_PORT_SHIFT) |
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(0xf << IOSF_BYTE_ENABLES_SHIFT) |
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(0 << IOSF_BAR_SHIFT) |
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IOSF_SB_BUSY);
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if (__intel_wait_for_register_fw(uncore,
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VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
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10000, 0, NULL) == 0) {
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if (is_read)
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*val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
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err = 0;
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} else {
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drm_dbg(&i915->drm, "IOSF sideband finish wait (%s) timed out\n",
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is_read ? "read" : "write");
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err = -ETIMEDOUT;
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}
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preempt_enable();
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return err;
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}
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u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
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SB_CRRDDA_NP, addr, &val);
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return val;
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}
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int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
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{
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return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
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SB_CRWRDA_NP, addr, &val);
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}
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u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
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{
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
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SB_CRWRDA_NP, reg, &val);
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}
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u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
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SB_CRRDDA_NP, addr, &val);
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return val;
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}
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u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_iosf_sb_write(struct drm_i915_private *i915,
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u8 port, u32 reg, u32 val)
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{
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
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SB_CRWRDA_NP, reg, &val);
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}
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u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
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{
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
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SB_CRWRDA_NP, reg, &val);
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}
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u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
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{
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
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SB_CRWRDA_NP, reg, &val);
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}
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static u32 vlv_dpio_phy_iosf_port(struct drm_i915_private *i915, enum dpio_phy phy)
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{
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/*
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* IOSF_PORT_DPIO: VLV x2 PHY (DP/HDMI B and C), CHV x1 PHY (DP/HDMI D)
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* IOSF_PORT_DPIO_2: CHV x2 PHY (DP/HDMI B and C)
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*/
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if (IS_CHERRYVIEW(i915))
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return phy == DPIO_PHY0 ? IOSF_PORT_DPIO_2 : IOSF_PORT_DPIO;
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else
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return IOSF_PORT_DPIO;
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}
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u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
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{
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u32 port = vlv_dpio_phy_iosf_port(i915, DPIO_PHY(pipe));
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u32 val = 0;
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vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
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/*
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* FIXME: There might be some registers where all 1's is a valid value,
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* so ideally we should check the register offset instead...
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*/
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drm_WARN(&i915->drm, val == 0xffffffff,
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"DPIO read pipe %c reg 0x%x == 0x%x\n",
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pipe_name(pipe), reg, val);
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return val;
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}
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void vlv_dpio_write(struct drm_i915_private *i915,
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enum pipe pipe, int reg, u32 val)
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{
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u32 port = vlv_dpio_phy_iosf_port(i915, DPIO_PHY(pipe));
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vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
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}
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u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
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reg, &val);
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return val;
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}
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void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
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{
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vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
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reg, &val);
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}
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