402 lines
10 KiB
C
402 lines
10 KiB
C
/*
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* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/ssbi.h>
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#include <linux/regmap.h>
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#include <linux/of_platform.h>
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#include <linux/mfd/core.h>
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#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
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#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
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#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
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#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
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#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
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#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
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#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
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#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
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#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
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#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
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#define PM_IRQF_LVL_SEL 0x01 /* level select */
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#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
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#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
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#define PM_IRQF_CLR 0x08 /* clear interrupt */
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#define PM_IRQF_BITS_MASK 0x70
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#define PM_IRQF_BITS_SHIFT 4
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#define PM_IRQF_WRITE 0x80
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#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
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PM_IRQF_MASK_RE)
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#define REG_HWREV 0x002 /* PMIC4 revision */
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#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
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#define PM8921_NR_IRQS 256
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struct pm_irq_chip {
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struct regmap *regmap;
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spinlock_t pm_irq_lock;
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struct irq_domain *irqdomain;
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unsigned int num_irqs;
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unsigned int num_blocks;
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unsigned int num_masters;
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u8 config[0];
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};
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static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
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unsigned int *ip)
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{
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int rc;
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spin_lock(&chip->pm_irq_lock);
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rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
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if (rc) {
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pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
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goto bail;
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}
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rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
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if (rc)
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pr_err("Failed Reading Status rc=%d\n", rc);
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bail:
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spin_unlock(&chip->pm_irq_lock);
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return rc;
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}
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static int
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pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
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{
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int rc;
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spin_lock(&chip->pm_irq_lock);
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rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
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if (rc) {
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pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
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goto bail;
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}
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cp |= PM_IRQF_WRITE;
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rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
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if (rc)
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pr_err("Failed Configuring IRQ rc=%d\n", rc);
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bail:
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spin_unlock(&chip->pm_irq_lock);
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return rc;
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}
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static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
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{
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int pmirq, irq, i, ret = 0;
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unsigned int bits;
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ret = pm8xxx_read_block_irq(chip, block, &bits);
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if (ret) {
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pr_err("Failed reading %d block ret=%d", block, ret);
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return ret;
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}
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if (!bits) {
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pr_err("block bit set in master but no irqs: %d", block);
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return 0;
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}
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/* Check IRQ bits */
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for (i = 0; i < 8; i++) {
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if (bits & (1 << i)) {
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pmirq = block * 8 + i;
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irq = irq_find_mapping(chip->irqdomain, pmirq);
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generic_handle_irq(irq);
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}
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}
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return 0;
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}
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static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
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{
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unsigned int blockbits;
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int block_number, i, ret = 0;
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ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
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&blockbits);
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if (ret) {
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pr_err("Failed to read master %d ret=%d\n", master, ret);
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return ret;
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}
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if (!blockbits) {
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pr_err("master bit set in root but no blocks: %d", master);
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return 0;
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}
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for (i = 0; i < 8; i++)
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if (blockbits & (1 << i)) {
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block_number = master * 8 + i; /* block # */
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ret |= pm8xxx_irq_block_handler(chip, block_number);
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}
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return ret;
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}
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static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
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struct irq_chip *irq_chip = irq_desc_get_chip(desc);
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unsigned int root;
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int i, ret, masters = 0;
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chained_irq_enter(irq_chip, desc);
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ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
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if (ret) {
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pr_err("Can't read root status ret=%d\n", ret);
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return;
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}
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/* on pm8xxx series masters start from bit 1 of the root */
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masters = root >> 1;
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/* Read allowed masters for blocks. */
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for (i = 0; i < chip->num_masters; i++)
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if (masters & (1 << i))
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pm8xxx_irq_master_handler(chip, i);
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chained_irq_exit(irq_chip, desc);
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}
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static void pm8xxx_irq_mask_ack(struct irq_data *d)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = irqd_to_hwirq(d);
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int irq_bit;
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u8 block, config;
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block = pmirq / 8;
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irq_bit = pmirq % 8;
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config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
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pm8xxx_config_irq(chip, block, config);
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}
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static void pm8xxx_irq_unmask(struct irq_data *d)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = irqd_to_hwirq(d);
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int irq_bit;
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u8 block, config;
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block = pmirq / 8;
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irq_bit = pmirq % 8;
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config = chip->config[pmirq];
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pm8xxx_config_irq(chip, block, config);
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}
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static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
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unsigned int pmirq = irqd_to_hwirq(d);
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int irq_bit;
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u8 block, config;
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block = pmirq / 8;
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irq_bit = pmirq % 8;
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chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
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| PM_IRQF_MASK_ALL;
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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if (flow_type & IRQF_TRIGGER_RISING)
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chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
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if (flow_type & IRQF_TRIGGER_FALLING)
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chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
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} else {
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chip->config[pmirq] |= PM_IRQF_LVL_SEL;
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if (flow_type & IRQF_TRIGGER_HIGH)
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chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
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else
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chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
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}
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config = chip->config[pmirq] | PM_IRQF_CLR;
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return pm8xxx_config_irq(chip, block, config);
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}
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static struct irq_chip pm8xxx_irq_chip = {
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.name = "pm8xxx",
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.irq_mask_ack = pm8xxx_irq_mask_ack,
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.irq_unmask = pm8xxx_irq_unmask,
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.irq_set_type = pm8xxx_irq_set_type,
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.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
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};
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static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct pm_irq_chip *chip = d->host_data;
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irq_set_chip_and_handler(irq, &pm8xxx_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, chip);
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#ifdef CONFIG_ARM
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set_irq_flags(irq, IRQF_VALID);
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#else
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irq_set_noprobe(irq);
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#endif
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return 0;
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}
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static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
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.xlate = irq_domain_xlate_twocell,
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.map = pm8xxx_irq_domain_map,
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};
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static const struct regmap_config ssbi_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0x3ff,
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.fast_io = true,
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.reg_read = ssbi_reg_read,
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.reg_write = ssbi_reg_write
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};
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static const struct of_device_id pm8921_id_table[] = {
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{ .compatible = "qcom,pm8058", },
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{ .compatible = "qcom,pm8921", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, pm8921_id_table);
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static int pm8921_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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int irq, rc;
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unsigned int val;
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u32 rev;
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struct pm_irq_chip *chip;
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unsigned int nirqs = PM8921_NR_IRQS;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
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&ssbi_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/* Read PMIC chip revision */
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rc = regmap_read(regmap, REG_HWREV, &val);
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if (rc) {
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pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
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return rc;
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}
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pr_info("PMIC revision 1: %02X\n", val);
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rev = val;
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/* Read PMIC chip revision 2 */
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rc = regmap_read(regmap, REG_HWREV_2, &val);
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if (rc) {
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pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
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REG_HWREV_2, rc);
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return rc;
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}
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pr_info("PMIC revision 2: %02X\n", val);
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rev |= val << BITS_PER_BYTE;
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip) +
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sizeof(chip->config[0]) * nirqs,
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GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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platform_set_drvdata(pdev, chip);
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chip->regmap = regmap;
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chip->num_irqs = nirqs;
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chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
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chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
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spin_lock_init(&chip->pm_irq_lock);
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chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, nirqs,
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&pm8xxx_irq_domain_ops,
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chip);
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if (!chip->irqdomain)
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return -ENODEV;
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irq_set_handler_data(irq, chip);
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irq_set_chained_handler(irq, pm8xxx_irq_handler);
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irq_set_irq_wake(irq, 1);
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rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
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if (rc) {
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irq_set_chained_handler(irq, NULL);
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irq_set_handler_data(irq, NULL);
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irq_domain_remove(chip->irqdomain);
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}
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return rc;
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}
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static int pm8921_remove_child(struct device *dev, void *unused)
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{
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platform_device_unregister(to_platform_device(dev));
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return 0;
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}
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static int pm8921_remove(struct platform_device *pdev)
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{
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int irq = platform_get_irq(pdev, 0);
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struct pm_irq_chip *chip = platform_get_drvdata(pdev);
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device_for_each_child(&pdev->dev, NULL, pm8921_remove_child);
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irq_set_chained_handler(irq, NULL);
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irq_set_handler_data(irq, NULL);
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irq_domain_remove(chip->irqdomain);
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return 0;
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}
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static struct platform_driver pm8921_driver = {
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.probe = pm8921_probe,
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.remove = pm8921_remove,
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.driver = {
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.name = "pm8921-core",
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.owner = THIS_MODULE,
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.of_match_table = pm8921_id_table,
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},
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};
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static int __init pm8921_init(void)
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{
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return platform_driver_register(&pm8921_driver);
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}
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subsys_initcall(pm8921_init);
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static void __exit pm8921_exit(void)
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{
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platform_driver_unregister(&pm8921_driver);
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}
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module_exit(pm8921_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("PMIC 8921 core driver");
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MODULE_VERSION("1.0");
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MODULE_ALIAS("platform:pm8921-core");
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