276 lines
8.2 KiB
C
276 lines
8.2 KiB
C
/*
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* Copyright © 2016-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/types.h>
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#include "intel_huc.h"
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#include "i915_drv.h"
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/**
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* DOC: HuC Firmware
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*
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* Motivation:
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* GEN9 introduces a new dedicated firmware for usage in media HEVC (High
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* Efficiency Video Coding) operations. Userspace can use the firmware
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* capabilities by adding HuC specific commands to batch buffers.
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*
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* Implementation:
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* The same firmware loader is used as the GuC. However, the actual
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* loading to HW is deferred until GEM initialization is done.
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*
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* Note that HuC firmware loading must be done before GuC loading.
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*/
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#define BXT_HUC_FW_MAJOR 01
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#define BXT_HUC_FW_MINOR 07
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#define BXT_BLD_NUM 1398
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#define SKL_HUC_FW_MAJOR 01
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#define SKL_HUC_FW_MINOR 07
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#define SKL_BLD_NUM 1398
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#define KBL_HUC_FW_MAJOR 02
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#define KBL_HUC_FW_MINOR 00
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#define KBL_BLD_NUM 1810
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#define GLK_HUC_FW_MAJOR 02
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#define GLK_HUC_FW_MINOR 00
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#define GLK_BLD_NUM 1748
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#define HUC_FW_PATH(platform, major, minor, bld_num) \
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"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
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__stringify(minor) "_" __stringify(bld_num) ".bin"
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#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
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SKL_HUC_FW_MINOR, SKL_BLD_NUM)
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MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
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#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
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BXT_HUC_FW_MINOR, BXT_BLD_NUM)
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MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
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#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
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KBL_HUC_FW_MINOR, KBL_BLD_NUM)
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MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
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#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
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GLK_HUC_FW_MINOR, GLK_BLD_NUM)
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/**
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* huc_ucode_xfer() - DMA's the firmware
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* @dev_priv: the drm_i915_private device
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*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* Return: 0 on success, non-zero on failure
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*/
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static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
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{
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struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
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struct i915_vma *vma;
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unsigned long offset = 0;
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u32 size;
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int ret;
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ret = i915_gem_object_set_to_gtt_domain(huc_fw->obj, false);
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if (ret) {
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DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
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return ret;
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}
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vma = i915_gem_object_ggtt_pin(huc_fw->obj, NULL, 0, 0,
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PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
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if (IS_ERR(vma)) {
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DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
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return PTR_ERR(vma);
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}
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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/* Set the source address for the uCode */
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offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
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I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
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I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
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/* Hardware doesn't look at destination address for HuC. Set it to 0,
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* but still program the correct address space.
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*/
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I915_WRITE(DMA_ADDR_1_LOW, 0);
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I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
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size = huc_fw->header_size + huc_fw->ucode_size;
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I915_WRITE(DMA_COPY_SIZE, size);
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/* Start the DMA */
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I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
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/* Wait for DMA to finish */
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ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
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DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
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/* Disable the bits once DMA is over */
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I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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/*
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* We keep the object pages for reuse during resume. But we can unpin it
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* now that DMA has completed, so it doesn't continue to take up space.
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*/
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i915_vma_unpin(vma);
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return ret;
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}
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/**
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* intel_huc_select_fw() - selects HuC firmware for loading
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* @huc: intel_huc struct
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*/
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void intel_huc_select_fw(struct intel_huc *huc)
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{
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struct drm_i915_private *dev_priv = huc_to_i915(huc);
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intel_uc_fw_init(&huc->fw, INTEL_UC_FW_TYPE_HUC);
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if (i915_modparams.huc_firmware_path) {
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huc->fw.path = i915_modparams.huc_firmware_path;
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huc->fw.major_ver_wanted = 0;
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huc->fw.minor_ver_wanted = 0;
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} else if (IS_SKYLAKE(dev_priv)) {
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huc->fw.path = I915_SKL_HUC_UCODE;
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huc->fw.major_ver_wanted = SKL_HUC_FW_MAJOR;
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huc->fw.minor_ver_wanted = SKL_HUC_FW_MINOR;
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} else if (IS_BROXTON(dev_priv)) {
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huc->fw.path = I915_BXT_HUC_UCODE;
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huc->fw.major_ver_wanted = BXT_HUC_FW_MAJOR;
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huc->fw.minor_ver_wanted = BXT_HUC_FW_MINOR;
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} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
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huc->fw.path = I915_KBL_HUC_UCODE;
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huc->fw.major_ver_wanted = KBL_HUC_FW_MAJOR;
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huc->fw.minor_ver_wanted = KBL_HUC_FW_MINOR;
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} else if (IS_GEMINILAKE(dev_priv)) {
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huc->fw.path = I915_GLK_HUC_UCODE;
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huc->fw.major_ver_wanted = GLK_HUC_FW_MAJOR;
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huc->fw.minor_ver_wanted = GLK_HUC_FW_MINOR;
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} else {
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DRM_ERROR("No HuC firmware known for platform with HuC!\n");
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return;
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}
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}
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/**
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* intel_huc_init_hw() - load HuC uCode to device
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* @huc: intel_huc structure
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*
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* Called from guc_setup() during driver loading and also after a GPU reset.
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* Be note that HuC loading must be done before GuC loading.
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*
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* The firmware image should have already been fetched into memory by the
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* earlier call to intel_huc_init(), so here we need only check that
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* is succeeded, and then transfer the image to the h/w.
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*
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*/
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void intel_huc_init_hw(struct intel_huc *huc)
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{
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struct drm_i915_private *dev_priv = huc_to_i915(huc);
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int err;
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DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
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huc->fw.path,
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intel_uc_fw_status_repr(huc->fw.fetch_status),
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intel_uc_fw_status_repr(huc->fw.load_status));
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if (huc->fw.fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
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return;
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huc->fw.load_status = INTEL_UC_FIRMWARE_PENDING;
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err = huc_ucode_xfer(dev_priv);
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huc->fw.load_status = err ?
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INTEL_UC_FIRMWARE_FAIL : INTEL_UC_FIRMWARE_SUCCESS;
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DRM_DEBUG_DRIVER("%s fw status: fetch %s, load %s\n",
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huc->fw.path,
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intel_uc_fw_status_repr(huc->fw.fetch_status),
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intel_uc_fw_status_repr(huc->fw.load_status));
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if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
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DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
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return;
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}
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/**
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* intel_huc_auth() - Authenticate HuC uCode
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* @huc: intel_huc structure
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*
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* Called after HuC and GuC firmware loading during intel_uc_init_hw().
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*
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* This function pins HuC firmware image object into GGTT.
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* Then it invokes GuC action to authenticate passing the offset to RSA
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* signature through intel_guc_auth_huc(). It then waits for 50ms for
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* firmware verification ACK and unpins the object.
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*/
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void intel_huc_auth(struct intel_huc *huc)
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{
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struct drm_i915_private *i915 = huc_to_i915(huc);
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struct intel_guc *guc = &i915->guc;
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struct i915_vma *vma;
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int ret;
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if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
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return;
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vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
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PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
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if (IS_ERR(vma)) {
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DRM_ERROR("failed to pin huc fw object %d\n",
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(int)PTR_ERR(vma));
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return;
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}
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ret = intel_guc_auth_huc(guc,
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guc_ggtt_offset(vma) + huc->fw.rsa_offset);
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if (ret) {
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DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
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goto out;
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}
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/* Check authentication status, it should be done by now */
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ret = intel_wait_for_register(i915,
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HUC_STATUS2,
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HUC_FW_VERIFIED,
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HUC_FW_VERIFIED,
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50);
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if (ret) {
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DRM_ERROR("HuC: Authentication failed %d\n", ret);
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goto out;
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}
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out:
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i915_vma_unpin(vma);
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}
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