Zhi Wang 5baa22c59f drm/i915: Introduce bit definitions of CTXT_SR_CTRL register. ... This patch introduces 2 bit definitions of context save/restore control register. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Suggested-by: Dave Gordon <david.s.gordon@intel.com> Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2015-02-13 23:28:22 +01:00
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drm	drm/i915: Introduce bit definitions of CTXT_SR_CTRL register.	2015-02-13 23:28:22 +01:00
host1x	gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register	2014-11-13 16:11:57 +01:00
ipu-v3	gpu: ipu-di: Switch to DIV_ROUND_CLOSEST for DI clock divider calc	2015-01-07 19:15:04 +01:00
vga	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2014-10-13 16:23:15 +02:00
Makefile	…