950 lines
26 KiB
C
950 lines
26 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* Authors: Christian König <christian.koenig@amd.com>
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_vce.h"
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#include "vid.h"
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#include "vce/vce_3_0_d.h"
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#include "vce/vce_3_0_sh_mask.h"
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#include "oss/oss_3_0_d.h"
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#include "oss/oss_3_0_sh_mask.h"
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#include "gca/gfx_8_0_d.h"
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#include "smu/smu_7_1_2_d.h"
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#include "smu/smu_7_1_2_sh_mask.h"
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#include "gca/gfx_8_0_d.h"
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#include "gca/gfx_8_0_sh_mask.h"
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#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
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#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
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#define GRBM_GFX_INDEX__VCE_ALL_PIPE 0x07
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618
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#define mmGRBM_GFX_INDEX_DEFAULT 0xE0000000
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#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
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#define VCE_V3_0_FW_SIZE (384 * 1024)
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#define VCE_V3_0_STACK_SIZE (64 * 1024)
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#define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024))
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#define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8))
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#define GET_VCE_INSTANCE(i) ((i) << GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT \
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| GRBM_GFX_INDEX__VCE_ALL_PIPE)
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static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
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static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
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static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
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static int vce_v3_0_wait_for_idle(void *handle);
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static int vce_v3_0_set_clockgating_state(void *handle,
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enum amd_clockgating_state state);
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/**
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* vce_v3_0_ring_get_rptr - get read pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware read pointer
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*/
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static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vce.ring[0])
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return RREG32(mmVCE_RB_RPTR);
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else if (ring == &adev->vce.ring[1])
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return RREG32(mmVCE_RB_RPTR2);
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else
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return RREG32(mmVCE_RB_RPTR3);
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}
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/**
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* vce_v3_0_ring_get_wptr - get write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware write pointer
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*/
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static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vce.ring[0])
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return RREG32(mmVCE_RB_WPTR);
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else if (ring == &adev->vce.ring[1])
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return RREG32(mmVCE_RB_WPTR2);
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else
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return RREG32(mmVCE_RB_WPTR3);
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}
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/**
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* vce_v3_0_ring_set_wptr - set write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Commits the write pointer to the hardware
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*/
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static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vce.ring[0])
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WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
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else if (ring == &adev->vce.ring[1])
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WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
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else
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WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
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}
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static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
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{
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WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0);
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}
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static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
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bool gated)
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{
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u32 data;
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/* Set Override to disable Clock Gating */
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vce_v3_0_override_vce_clock_gating(adev, true);
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/* This function enables MGCG which is controlled by firmware.
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With the clocks in the gated state the core is still
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accessible but the firmware will throttle the clocks on the
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fly as necessary.
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*/
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if (!gated) {
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data = RREG32(mmVCE_CLOCK_GATING_B);
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data |= 0x1ff;
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data &= ~0xef0000;
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WREG32(mmVCE_CLOCK_GATING_B, data);
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data = RREG32(mmVCE_UENC_CLOCK_GATING);
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data |= 0x3ff000;
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data &= ~0xffc00000;
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WREG32(mmVCE_UENC_CLOCK_GATING, data);
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data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
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data |= 0x2;
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data &= ~0x00010000;
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WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
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data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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data |= 0x37f;
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
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data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
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data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
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VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
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VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK |
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0x8;
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WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
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} else {
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data = RREG32(mmVCE_CLOCK_GATING_B);
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data &= ~0x80010;
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data |= 0xe70008;
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WREG32(mmVCE_CLOCK_GATING_B, data);
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data = RREG32(mmVCE_UENC_CLOCK_GATING);
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data |= 0xffc00000;
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WREG32(mmVCE_UENC_CLOCK_GATING, data);
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data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
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data |= 0x10000;
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WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
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data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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data &= ~0x3ff;
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
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data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
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data &= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK |
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VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK |
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VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK |
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0x8);
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WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
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}
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vce_v3_0_override_vce_clock_gating(adev, false);
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}
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static int vce_v3_0_firmware_loaded(struct amdgpu_device *adev)
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{
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int i, j;
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for (i = 0; i < 10; ++i) {
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for (j = 0; j < 100; ++j) {
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uint32_t status = RREG32(mmVCE_STATUS);
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if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
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return 0;
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mdelay(10);
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}
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DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
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WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
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mdelay(10);
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WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
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mdelay(10);
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}
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return -ETIMEDOUT;
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}
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/**
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* vce_v3_0_start - start VCE block
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*
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* @adev: amdgpu_device pointer
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*
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* Setup and start the VCE block
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*/
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static int vce_v3_0_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring;
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int idx, r;
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ring = &adev->vce.ring[0];
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WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
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ring = &adev->vce.ring[1];
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WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
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ring = &adev->vce.ring[2];
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WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
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WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
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mutex_lock(&adev->grbm_idx_mutex);
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for (idx = 0; idx < 2; ++idx) {
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if (adev->vce.harvest_config & (1 << idx))
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continue;
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
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vce_v3_0_mc_resume(adev, idx);
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WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1);
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if (adev->asic_type >= CHIP_STONEY)
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WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
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else
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WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
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WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
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mdelay(100);
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r = vce_v3_0_firmware_loaded(adev);
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/* clear BUSY flag */
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WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0);
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if (r) {
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DRM_ERROR("VCE not responding, giving up!!!\n");
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mutex_unlock(&adev->grbm_idx_mutex);
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return r;
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}
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}
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WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
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mutex_unlock(&adev->grbm_idx_mutex);
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return 0;
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}
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static int vce_v3_0_stop(struct amdgpu_device *adev)
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{
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int idx;
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mutex_lock(&adev->grbm_idx_mutex);
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for (idx = 0; idx < 2; ++idx) {
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if (adev->vce.harvest_config & (1 << idx))
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continue;
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WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
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if (adev->asic_type >= CHIP_STONEY)
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WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001);
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else
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WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0);
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/* hold on ECPU */
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WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
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/* clear VCE STATUS */
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WREG32(mmVCE_STATUS, 0);
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}
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WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
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mutex_unlock(&adev->grbm_idx_mutex);
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return 0;
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}
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#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
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#define VCE_HARVEST_FUSE_MACRO__SHIFT 27
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#define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000
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static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
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{
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u32 tmp;
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/* Fiji, Stoney, Polaris10, Polaris11, Polaris12 are single pipe */
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if ((adev->asic_type == CHIP_FIJI) ||
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(adev->asic_type == CHIP_STONEY) ||
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(adev->asic_type == CHIP_POLARIS10) ||
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(adev->asic_type == CHIP_POLARIS11) ||
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(adev->asic_type == CHIP_POLARIS12))
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return AMDGPU_VCE_HARVEST_VCE1;
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/* Tonga and CZ are dual or single pipe */
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if (adev->flags & AMD_IS_APU)
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tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
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VCE_HARVEST_FUSE_MACRO__MASK) >>
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VCE_HARVEST_FUSE_MACRO__SHIFT;
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else
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tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
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CC_HARVEST_FUSES__VCE_DISABLE_MASK) >>
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CC_HARVEST_FUSES__VCE_DISABLE__SHIFT;
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switch (tmp) {
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case 1:
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return AMDGPU_VCE_HARVEST_VCE0;
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case 2:
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return AMDGPU_VCE_HARVEST_VCE1;
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case 3:
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return AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
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default:
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return 0;
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}
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}
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static int vce_v3_0_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);
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if ((adev->vce.harvest_config &
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(AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) ==
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(AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1))
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return -ENOENT;
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adev->vce.num_rings = 3;
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vce_v3_0_set_ring_funcs(adev);
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vce_v3_0_set_irq_funcs(adev);
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return 0;
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}
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static int vce_v3_0_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_ring *ring;
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int r, i;
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/* VCE */
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r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 167, &adev->vce.irq);
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if (r)
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return r;
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r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE +
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(VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2);
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if (r)
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return r;
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/* 52.8.3 required for 3 ring support */
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if (adev->vce.fw_version < FW_52_8_3)
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adev->vce.num_rings = 2;
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r = amdgpu_vce_resume(adev);
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if (r)
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return r;
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for (i = 0; i < adev->vce.num_rings; i++) {
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ring = &adev->vce.ring[i];
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sprintf(ring->name, "vce%d", i);
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r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
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if (r)
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return r;
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}
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return r;
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}
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static int vce_v3_0_sw_fini(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = amdgpu_vce_suspend(adev);
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if (r)
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return r;
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return amdgpu_vce_sw_fini(adev);
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}
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static int vce_v3_0_hw_init(void *handle)
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{
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int r, i;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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vce_v3_0_override_vce_clock_gating(adev, true);
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if (!(adev->flags & AMD_IS_APU))
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amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
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for (i = 0; i < adev->vce.num_rings; i++)
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adev->vce.ring[i].ready = false;
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for (i = 0; i < adev->vce.num_rings; i++) {
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r = amdgpu_ring_test_ring(&adev->vce.ring[i]);
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if (r)
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return r;
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else
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adev->vce.ring[i].ready = true;
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}
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DRM_INFO("VCE initialized successfully.\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vce_v3_0_hw_fini(void *handle)
|
|
{
|
|
int r;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
r = vce_v3_0_wait_for_idle(handle);
|
|
if (r)
|
|
return r;
|
|
|
|
vce_v3_0_stop(adev);
|
|
return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
|
|
}
|
|
|
|
static int vce_v3_0_suspend(void *handle)
|
|
{
|
|
int r;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
r = vce_v3_0_hw_fini(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
return amdgpu_vce_suspend(adev);
|
|
}
|
|
|
|
static int vce_v3_0_resume(void *handle)
|
|
{
|
|
int r;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
r = amdgpu_vce_resume(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
return vce_v3_0_hw_init(adev);
|
|
}
|
|
|
|
static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
|
|
{
|
|
uint32_t offset, size;
|
|
|
|
WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
|
|
WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
|
|
WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
|
|
WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);
|
|
|
|
WREG32(mmVCE_LMI_CTRL, 0x00398000);
|
|
WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
|
|
WREG32(mmVCE_LMI_SWAP_CNTL, 0);
|
|
WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
|
|
WREG32(mmVCE_LMI_VM_CTRL, 0);
|
|
WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000);
|
|
|
|
if (adev->asic_type >= CHIP_STONEY) {
|
|
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
|
|
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
|
|
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));
|
|
} else
|
|
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
|
|
offset = AMDGPU_VCE_FIRMWARE_OFFSET;
|
|
size = VCE_V3_0_FW_SIZE;
|
|
WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
|
|
WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
|
|
|
|
if (idx == 0) {
|
|
offset += size;
|
|
size = VCE_V3_0_STACK_SIZE;
|
|
WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
|
|
WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
|
|
offset += size;
|
|
size = VCE_V3_0_DATA_SIZE;
|
|
WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
|
|
WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
|
|
} else {
|
|
offset += size + VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE;
|
|
size = VCE_V3_0_STACK_SIZE;
|
|
WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);
|
|
WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
|
|
offset += size;
|
|
size = VCE_V3_0_DATA_SIZE;
|
|
WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff);
|
|
WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
|
|
}
|
|
|
|
WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
|
|
WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
|
|
}
|
|
|
|
static bool vce_v3_0_is_idle(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
u32 mask = 0;
|
|
|
|
mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
|
|
mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;
|
|
|
|
return !(RREG32(mmSRBM_STATUS2) & mask);
|
|
}
|
|
|
|
static int vce_v3_0_wait_for_idle(void *handle)
|
|
{
|
|
unsigned i;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
for (i = 0; i < adev->usec_timeout; i++)
|
|
if (vce_v3_0_is_idle(handle))
|
|
return 0;
|
|
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
#define VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK 0x00000008L /* AUTO_BUSY */
|
|
#define VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK 0x00000010L /* RB0_BUSY */
|
|
#define VCE_STATUS_VCPU_REPORT_RB1_BUSY_MASK 0x00000020L /* RB1_BUSY */
|
|
#define AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \
|
|
VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK)
|
|
|
|
static bool vce_v3_0_check_soft_reset(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
u32 srbm_soft_reset = 0;
|
|
|
|
/* According to VCE team , we should use VCE_STATUS instead
|
|
* SRBM_STATUS.VCE_BUSY bit for busy status checking.
|
|
* GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE
|
|
* instance's registers are accessed
|
|
* (0 for 1st instance, 10 for 2nd instance).
|
|
*
|
|
*VCE_STATUS
|
|
*|UENC|ACPI|AUTO ACTIVE|RB1 |RB0 |RB2 | |FW_LOADED|JOB |
|
|
*|----+----+-----------+----+----+----+----------+---------+----|
|
|
*|bit8|bit7| bit6 |bit5|bit4|bit3| bit2 | bit1 |bit0|
|
|
*
|
|
* VCE team suggest use bit 3--bit 6 for busy status check
|
|
*/
|
|
mutex_lock(&adev->grbm_idx_mutex);
|
|
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
|
|
if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
|
|
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
|
|
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
|
|
}
|
|
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
|
|
if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
|
|
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
|
|
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
|
|
}
|
|
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
|
|
mutex_unlock(&adev->grbm_idx_mutex);
|
|
|
|
if (srbm_soft_reset) {
|
|
adev->vce.srbm_soft_reset = srbm_soft_reset;
|
|
return true;
|
|
} else {
|
|
adev->vce.srbm_soft_reset = 0;
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static int vce_v3_0_soft_reset(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
u32 srbm_soft_reset;
|
|
|
|
if (!adev->vce.srbm_soft_reset)
|
|
return 0;
|
|
srbm_soft_reset = adev->vce.srbm_soft_reset;
|
|
|
|
if (srbm_soft_reset) {
|
|
u32 tmp;
|
|
|
|
tmp = RREG32(mmSRBM_SOFT_RESET);
|
|
tmp |= srbm_soft_reset;
|
|
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
|
|
WREG32(mmSRBM_SOFT_RESET, tmp);
|
|
tmp = RREG32(mmSRBM_SOFT_RESET);
|
|
|
|
udelay(50);
|
|
|
|
tmp &= ~srbm_soft_reset;
|
|
WREG32(mmSRBM_SOFT_RESET, tmp);
|
|
tmp = RREG32(mmSRBM_SOFT_RESET);
|
|
|
|
/* Wait a little for things to settle down */
|
|
udelay(50);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vce_v3_0_pre_soft_reset(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
if (!adev->vce.srbm_soft_reset)
|
|
return 0;
|
|
|
|
mdelay(5);
|
|
|
|
return vce_v3_0_suspend(adev);
|
|
}
|
|
|
|
|
|
static int vce_v3_0_post_soft_reset(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
if (!adev->vce.srbm_soft_reset)
|
|
return 0;
|
|
|
|
mdelay(5);
|
|
|
|
return vce_v3_0_resume(adev);
|
|
}
|
|
|
|
static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *source,
|
|
unsigned type,
|
|
enum amdgpu_interrupt_state state)
|
|
{
|
|
uint32_t val = 0;
|
|
|
|
if (state == AMDGPU_IRQ_STATE_ENABLE)
|
|
val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
|
|
|
|
WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
|
|
return 0;
|
|
}
|
|
|
|
static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *source,
|
|
struct amdgpu_iv_entry *entry)
|
|
{
|
|
DRM_DEBUG("IH: VCE\n");
|
|
|
|
WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1);
|
|
|
|
switch (entry->src_data[0]) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);
|
|
break;
|
|
default:
|
|
DRM_ERROR("Unhandled interrupt: %d %d\n",
|
|
entry->src_id, entry->src_data[0]);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vce_v3_0_set_clockgating_state(void *handle,
|
|
enum amd_clockgating_state state)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
|
|
int i;
|
|
|
|
if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
|
|
return 0;
|
|
|
|
mutex_lock(&adev->grbm_idx_mutex);
|
|
for (i = 0; i < 2; i++) {
|
|
/* Program VCE Instance 0 or 1 if not harvested */
|
|
if (adev->vce.harvest_config & (1 << i))
|
|
continue;
|
|
|
|
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i));
|
|
|
|
if (!enable) {
|
|
/* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */
|
|
uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);
|
|
data &= ~(0xf | 0xff0);
|
|
data |= ((0x0 << 0) | (0x04 << 4));
|
|
WREG32(mmVCE_CLOCK_GATING_A, data);
|
|
|
|
/* initialize VCE_UENC_CLOCK_GATING: Clock ON/OFF delay */
|
|
data = RREG32(mmVCE_UENC_CLOCK_GATING);
|
|
data &= ~(0xf | 0xff0);
|
|
data |= ((0x0 << 0) | (0x04 << 4));
|
|
WREG32(mmVCE_UENC_CLOCK_GATING, data);
|
|
}
|
|
|
|
vce_v3_0_set_vce_sw_clock_gating(adev, enable);
|
|
}
|
|
|
|
WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
|
|
mutex_unlock(&adev->grbm_idx_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vce_v3_0_set_powergating_state(void *handle,
|
|
enum amd_powergating_state state)
|
|
{
|
|
/* This doesn't actually powergate the VCE block.
|
|
* That's done in the dpm code via the SMC. This
|
|
* just re-inits the block as necessary. The actual
|
|
* gating still happens in the dpm code. We should
|
|
* revisit this when there is a cleaner line between
|
|
* the smc and the hw blocks
|
|
*/
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
int ret = 0;
|
|
|
|
if (state == AMD_PG_STATE_GATE) {
|
|
ret = vce_v3_0_stop(adev);
|
|
if (ret)
|
|
goto out;
|
|
} else {
|
|
ret = vce_v3_0_start(adev);
|
|
if (ret)
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
int data;
|
|
|
|
mutex_lock(&adev->pm.mutex);
|
|
|
|
if (adev->flags & AMD_IS_APU)
|
|
data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
|
|
else
|
|
data = RREG32_SMC(ixCURRENT_PG_STATUS);
|
|
|
|
if (data & CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) {
|
|
DRM_INFO("Cannot get clockgating state when VCE is powergated.\n");
|
|
goto out;
|
|
}
|
|
|
|
WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
|
|
|
|
/* AMD_CG_SUPPORT_VCE_MGCG */
|
|
data = RREG32(mmVCE_CLOCK_GATING_A);
|
|
if (data & (0x04 << 4))
|
|
*flags |= AMD_CG_SUPPORT_VCE_MGCG;
|
|
|
|
out:
|
|
mutex_unlock(&adev->pm.mutex);
|
|
}
|
|
|
|
static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
|
|
struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
|
|
{
|
|
amdgpu_ring_write(ring, VCE_CMD_IB_VM);
|
|
amdgpu_ring_write(ring, vm_id);
|
|
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
|
|
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
|
|
amdgpu_ring_write(ring, ib->length_dw);
|
|
}
|
|
|
|
static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring,
|
|
unsigned int vm_id, uint64_t pd_addr)
|
|
{
|
|
amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB);
|
|
amdgpu_ring_write(ring, vm_id);
|
|
amdgpu_ring_write(ring, pd_addr >> 12);
|
|
|
|
amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB);
|
|
amdgpu_ring_write(ring, vm_id);
|
|
amdgpu_ring_write(ring, VCE_CMD_END);
|
|
}
|
|
|
|
static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring)
|
|
{
|
|
uint32_t seq = ring->fence_drv.sync_seq;
|
|
uint64_t addr = ring->fence_drv.gpu_addr;
|
|
|
|
amdgpu_ring_write(ring, VCE_CMD_WAIT_GE);
|
|
amdgpu_ring_write(ring, lower_32_bits(addr));
|
|
amdgpu_ring_write(ring, upper_32_bits(addr));
|
|
amdgpu_ring_write(ring, seq);
|
|
}
|
|
|
|
static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
|
|
.name = "vce_v3_0",
|
|
.early_init = vce_v3_0_early_init,
|
|
.late_init = NULL,
|
|
.sw_init = vce_v3_0_sw_init,
|
|
.sw_fini = vce_v3_0_sw_fini,
|
|
.hw_init = vce_v3_0_hw_init,
|
|
.hw_fini = vce_v3_0_hw_fini,
|
|
.suspend = vce_v3_0_suspend,
|
|
.resume = vce_v3_0_resume,
|
|
.is_idle = vce_v3_0_is_idle,
|
|
.wait_for_idle = vce_v3_0_wait_for_idle,
|
|
.check_soft_reset = vce_v3_0_check_soft_reset,
|
|
.pre_soft_reset = vce_v3_0_pre_soft_reset,
|
|
.soft_reset = vce_v3_0_soft_reset,
|
|
.post_soft_reset = vce_v3_0_post_soft_reset,
|
|
.set_clockgating_state = vce_v3_0_set_clockgating_state,
|
|
.set_powergating_state = vce_v3_0_set_powergating_state,
|
|
.get_clockgating_state = vce_v3_0_get_clockgating_state,
|
|
};
|
|
|
|
static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
|
|
.type = AMDGPU_RING_TYPE_VCE,
|
|
.align_mask = 0xf,
|
|
.nop = VCE_CMD_NO_OP,
|
|
.support_64bit_ptrs = false,
|
|
.get_rptr = vce_v3_0_ring_get_rptr,
|
|
.get_wptr = vce_v3_0_ring_get_wptr,
|
|
.set_wptr = vce_v3_0_ring_set_wptr,
|
|
.parse_cs = amdgpu_vce_ring_parse_cs,
|
|
.emit_frame_size =
|
|
4 + /* vce_v3_0_emit_pipeline_sync */
|
|
6, /* amdgpu_vce_ring_emit_fence x1 no user fence */
|
|
.emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */
|
|
.emit_ib = amdgpu_vce_ring_emit_ib,
|
|
.emit_fence = amdgpu_vce_ring_emit_fence,
|
|
.test_ring = amdgpu_vce_ring_test_ring,
|
|
.test_ib = amdgpu_vce_ring_test_ib,
|
|
.insert_nop = amdgpu_ring_insert_nop,
|
|
.pad_ib = amdgpu_ring_generic_pad_ib,
|
|
.begin_use = amdgpu_vce_ring_begin_use,
|
|
.end_use = amdgpu_vce_ring_end_use,
|
|
};
|
|
|
|
static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = {
|
|
.type = AMDGPU_RING_TYPE_VCE,
|
|
.align_mask = 0xf,
|
|
.nop = VCE_CMD_NO_OP,
|
|
.support_64bit_ptrs = false,
|
|
.get_rptr = vce_v3_0_ring_get_rptr,
|
|
.get_wptr = vce_v3_0_ring_get_wptr,
|
|
.set_wptr = vce_v3_0_ring_set_wptr,
|
|
.parse_cs = amdgpu_vce_ring_parse_cs_vm,
|
|
.emit_frame_size =
|
|
6 + /* vce_v3_0_emit_vm_flush */
|
|
4 + /* vce_v3_0_emit_pipeline_sync */
|
|
6 + 6, /* amdgpu_vce_ring_emit_fence x2 vm fence */
|
|
.emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */
|
|
.emit_ib = vce_v3_0_ring_emit_ib,
|
|
.emit_vm_flush = vce_v3_0_emit_vm_flush,
|
|
.emit_pipeline_sync = vce_v3_0_emit_pipeline_sync,
|
|
.emit_fence = amdgpu_vce_ring_emit_fence,
|
|
.test_ring = amdgpu_vce_ring_test_ring,
|
|
.test_ib = amdgpu_vce_ring_test_ib,
|
|
.insert_nop = amdgpu_ring_insert_nop,
|
|
.pad_ib = amdgpu_ring_generic_pad_ib,
|
|
.begin_use = amdgpu_vce_ring_begin_use,
|
|
.end_use = amdgpu_vce_ring_end_use,
|
|
};
|
|
|
|
static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
|
|
{
|
|
int i;
|
|
|
|
if (adev->asic_type >= CHIP_STONEY) {
|
|
for (i = 0; i < adev->vce.num_rings; i++)
|
|
adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs;
|
|
DRM_INFO("VCE enabled in VM mode\n");
|
|
} else {
|
|
for (i = 0; i < adev->vce.num_rings; i++)
|
|
adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs;
|
|
DRM_INFO("VCE enabled in physical mode\n");
|
|
}
|
|
}
|
|
|
|
static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = {
|
|
.set = vce_v3_0_set_interrupt_state,
|
|
.process = vce_v3_0_process_interrupt,
|
|
};
|
|
|
|
static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev)
|
|
{
|
|
adev->vce.irq.num_types = 1;
|
|
adev->vce.irq.funcs = &vce_v3_0_irq_funcs;
|
|
};
|
|
|
|
const struct amdgpu_ip_block_version vce_v3_0_ip_block =
|
|
{
|
|
.type = AMD_IP_BLOCK_TYPE_VCE,
|
|
.major = 3,
|
|
.minor = 0,
|
|
.rev = 0,
|
|
.funcs = &vce_v3_0_ip_funcs,
|
|
};
|
|
|
|
const struct amdgpu_ip_block_version vce_v3_1_ip_block =
|
|
{
|
|
.type = AMD_IP_BLOCK_TYPE_VCE,
|
|
.major = 3,
|
|
.minor = 1,
|
|
.rev = 0,
|
|
.funcs = &vce_v3_0_ip_funcs,
|
|
};
|
|
|
|
const struct amdgpu_ip_block_version vce_v3_4_ip_block =
|
|
{
|
|
.type = AMD_IP_BLOCK_TYPE_VCE,
|
|
.major = 3,
|
|
.minor = 4,
|
|
.rev = 0,
|
|
.funcs = &vce_v3_0_ip_funcs,
|
|
};
|