350 lines
8.7 KiB
Plaintext
350 lines
8.7 KiB
Plaintext
/*
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* Copyright 2013 CompuLab Ltd.
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* Copyright 2016 Christopher Spinrath
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*
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* Based on the devicetree distributed with the vendor kernel for the
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* Utilite Pro:
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* Copyright 2013 CompuLab Ltd.
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* Author: Valentin Raevsky <valentin@compulab.co.il>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/input/input.h>
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#include "imx6q-cm-fx6.dts"
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/ {
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model = "CompuLab Utilite Pro";
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compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q";
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aliases {
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ethernet1 = ð1;
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rtc0 = &em3027;
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rtc1 = &snvs_rtc;
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};
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encoder {
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compatible = "ti,tfp410";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tfp410_in: endpoint {
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remote-endpoint = <¶llel_display_out>;
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};
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};
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port@1 {
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reg = <1>;
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tfp410_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_keys>;
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power {
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label = "Power Button";
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gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_POWER>;
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wakeup-source;
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};
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};
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hdmi-connector {
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compatible = "hdmi-connector";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hpd>;
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type = "a";
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ddc-i2c-bus = <&i2c_dvi_ddc>;
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hpd-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&tfp410_out>;
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};
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};
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};
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i2cmux {
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compatible = "i2c-mux-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1mux>;
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#address-cells = <1>;
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#size-cells = <0>;
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mux-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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i2c-parent = <&i2c1>;
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i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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em3027: rtc@56 {
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compatible = "emmicro,em3027";
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reg = <0x56>;
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};
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};
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i2c_dvi_ddc: i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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parallel-display {
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compatible = "fsl,imx-parallel-display";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1>;
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interface-pix-fmt = "rgb24";
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port@0 {
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reg = <0>;
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parallel_display_in: endpoint {
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remote-endpoint = <&ipu1_di0_disp0>;
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};
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};
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port@1 {
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reg = <1>;
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parallel_display_out: endpoint {
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remote-endpoint = <&tfp410_in>;
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};
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};
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};
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};
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/*
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* A single IPU is not able to drive both display interfaces available on the
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* Utilite Pro at high resolution due to its bandwidth limitation. Since the
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* tfp410 encoder is wired up to IPU1, sever the link between IPU1 and the
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* SoC-internal Designware HDMI encoder forcing the latter to be connected to
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* IPU2 instead of IPU1.
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*/
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/delete-node/&ipu1_di0_hdmi;
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/delete-node/&hdmi_mux_0;
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/delete-node/&ipu1_di1_hdmi;
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/delete-node/&hdmi_mux_1;
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&hdmi {
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ddc-i2c-bus = <&i2c2>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_gpio_keys: gpio_keysgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
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>;
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};
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pinctrl_hpd: hpdgrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c1mux: i2c1muxgrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
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MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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>;
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};
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pinctrl_ipu1: ipu1grp {
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
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MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
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MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
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MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
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MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
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MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
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MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
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MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
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MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
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MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
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MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
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MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
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MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
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MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
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MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
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MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
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MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
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MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
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MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
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MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
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MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
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MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
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MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
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MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
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MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
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MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
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MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
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MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
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MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
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MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
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MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
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>;
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};
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};
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&ipu1_di0_disp0 {
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remote-endpoint = <¶llel_display_in>;
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};
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&pcie {
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pcie@0,0 {
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reg = <0x000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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/* non-removable i211 ethernet card */
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eth1: intel,i211@pcie0,0 {
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reg = <0x010000 0 0 0 0>;
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};
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};
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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uart-has-rtscts;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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no-1-8-v;
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broken-cd;
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keep-power-in-suspend;
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status = "okay";
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};
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