437 lines
12 KiB
C
437 lines
12 KiB
C
/*
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* Macros and prototypes for i.MX21
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*
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* Copyright (C) 2006 Loping Dog Embedded Systems
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* Copyright (C) 2009 Martin Fuzzey
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* Originally written by Jay Monkman <jtm@lopingdog.com>
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* Ported to 2.6.30, debugged and enhanced by Martin Fuzzey
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __LINUX_IMX21_HCD_H__
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#define __LINUX_IMX21_HCD_H__
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#include <mach/mx21-usbhost.h>
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#define NUM_ISO_ETDS 2
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#define USB_NUM_ETD 32
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#define DMEM_SIZE 4096
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/* Register definitions */
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#define USBOTG_HWMODE 0x00
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#define USBOTG_HWMODE_ANASDBEN (1 << 14)
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#define USBOTG_HWMODE_OTGXCVR_SHIFT 6
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#define USBOTG_HWMODE_OTGXCVR_MASK (3 << 6)
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#define USBOTG_HWMODE_OTGXCVR_TD_RD (0 << 6)
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#define USBOTG_HWMODE_OTGXCVR_TS_RD (2 << 6)
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#define USBOTG_HWMODE_OTGXCVR_TD_RS (1 << 6)
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#define USBOTG_HWMODE_OTGXCVR_TS_RS (3 << 6)
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#define USBOTG_HWMODE_HOSTXCVR_SHIFT 4
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#define USBOTG_HWMODE_HOSTXCVR_MASK (3 << 4)
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#define USBOTG_HWMODE_HOSTXCVR_TD_RD (0 << 4)
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#define USBOTG_HWMODE_HOSTXCVR_TS_RD (2 << 4)
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#define USBOTG_HWMODE_HOSTXCVR_TD_RS (1 << 4)
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#define USBOTG_HWMODE_HOSTXCVR_TS_RS (3 << 4)
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#define USBOTG_HWMODE_CRECFG_MASK (3 << 0)
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#define USBOTG_HWMODE_CRECFG_HOST (1 << 0)
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#define USBOTG_HWMODE_CRECFG_FUNC (2 << 0)
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#define USBOTG_HWMODE_CRECFG_HNP (3 << 0)
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#define USBOTG_CINT_STAT 0x04
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#define USBOTG_CINT_STEN 0x08
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#define USBOTG_ASHNPINT (1 << 5)
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#define USBOTG_ASFCINT (1 << 4)
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#define USBOTG_ASHCINT (1 << 3)
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#define USBOTG_SHNPINT (1 << 2)
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#define USBOTG_FCINT (1 << 1)
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#define USBOTG_HCINT (1 << 0)
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#define USBOTG_CLK_CTRL 0x0c
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#define USBOTG_CLK_CTRL_FUNC (1 << 2)
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#define USBOTG_CLK_CTRL_HST (1 << 1)
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#define USBOTG_CLK_CTRL_MAIN (1 << 0)
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#define USBOTG_RST_CTRL 0x10
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#define USBOTG_RST_RSTI2C (1 << 15)
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#define USBOTG_RST_RSTCTRL (1 << 5)
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#define USBOTG_RST_RSTFC (1 << 4)
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#define USBOTG_RST_RSTFSKE (1 << 3)
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#define USBOTG_RST_RSTRH (1 << 2)
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#define USBOTG_RST_RSTHSIE (1 << 1)
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#define USBOTG_RST_RSTHC (1 << 0)
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#define USBOTG_FRM_INTVL 0x14
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#define USBOTG_FRM_REMAIN 0x18
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#define USBOTG_HNP_CSR 0x1c
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#define USBOTG_HNP_ISR 0x2c
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#define USBOTG_HNP_IEN 0x30
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#define USBOTG_I2C_TXCVR_REG(x) (0x100 + (x))
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#define USBOTG_I2C_XCVR_DEVAD 0x118
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#define USBOTG_I2C_SEQ_OP_REG 0x119
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#define USBOTG_I2C_SEQ_RD_STARTAD 0x11a
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#define USBOTG_I2C_OP_CTRL_REG 0x11b
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#define USBOTG_I2C_SCLK_TO_SCK_HPER 0x11e
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#define USBOTG_I2C_MASTER_INT_REG 0x11f
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#define USBH_HOST_CTRL 0x80
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#define USBH_HOST_CTRL_HCRESET (1 << 31)
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#define USBH_HOST_CTRL_SCHDOVR(x) ((x) << 16)
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#define USBH_HOST_CTRL_RMTWUEN (1 << 4)
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#define USBH_HOST_CTRL_HCUSBSTE_RESET (0 << 2)
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#define USBH_HOST_CTRL_HCUSBSTE_RESUME (1 << 2)
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#define USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL (2 << 2)
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#define USBH_HOST_CTRL_HCUSBSTE_SUSPEND (3 << 2)
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#define USBH_HOST_CTRL_CTLBLKSR_1 (0 << 0)
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#define USBH_HOST_CTRL_CTLBLKSR_2 (1 << 0)
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#define USBH_HOST_CTRL_CTLBLKSR_3 (2 << 0)
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#define USBH_HOST_CTRL_CTLBLKSR_4 (3 << 0)
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#define USBH_SYSISR 0x88
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#define USBH_SYSISR_PSCINT (1 << 6)
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#define USBH_SYSISR_FMOFINT (1 << 5)
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#define USBH_SYSISR_HERRINT (1 << 4)
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#define USBH_SYSISR_RESDETINT (1 << 3)
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#define USBH_SYSISR_SOFINT (1 << 2)
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#define USBH_SYSISR_DONEINT (1 << 1)
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#define USBH_SYSISR_SORINT (1 << 0)
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#define USBH_SYSIEN 0x8c
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#define USBH_SYSIEN_PSCINT (1 << 6)
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#define USBH_SYSIEN_FMOFINT (1 << 5)
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#define USBH_SYSIEN_HERRINT (1 << 4)
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#define USBH_SYSIEN_RESDETINT (1 << 3)
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#define USBH_SYSIEN_SOFINT (1 << 2)
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#define USBH_SYSIEN_DONEINT (1 << 1)
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#define USBH_SYSIEN_SORINT (1 << 0)
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#define USBH_XBUFSTAT 0x98
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#define USBH_YBUFSTAT 0x9c
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#define USBH_XYINTEN 0xa0
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#define USBH_XFILLSTAT 0xa8
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#define USBH_YFILLSTAT 0xac
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#define USBH_ETDENSET 0xc0
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#define USBH_ETDENCLR 0xc4
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#define USBH_IMMEDINT 0xcc
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#define USBH_ETDDONESTAT 0xd0
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#define USBH_ETDDONEEN 0xd4
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#define USBH_FRMNUB 0xe0
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#define USBH_LSTHRESH 0xe4
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#define USBH_ROOTHUBA 0xe8
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#define USBH_ROOTHUBA_PWRTOGOOD_MASK (0xff)
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#define USBH_ROOTHUBA_PWRTOGOOD_SHIFT (24)
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#define USBH_ROOTHUBA_NOOVRCURP (1 << 12)
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#define USBH_ROOTHUBA_OVRCURPM (1 << 11)
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#define USBH_ROOTHUBA_DEVTYPE (1 << 10)
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#define USBH_ROOTHUBA_PWRSWTMD (1 << 9)
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#define USBH_ROOTHUBA_NOPWRSWT (1 << 8)
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#define USBH_ROOTHUBA_NDNSTMPRT_MASK (0xff)
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#define USBH_ROOTHUBB 0xec
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#define USBH_ROOTHUBB_PRTPWRCM(x) (1 << ((x) + 16))
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#define USBH_ROOTHUBB_DEVREMOVE(x) (1 << (x))
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#define USBH_ROOTSTAT 0xf0
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#define USBH_ROOTSTAT_CLRRMTWUE (1 << 31)
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#define USBH_ROOTSTAT_OVRCURCHG (1 << 17)
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#define USBH_ROOTSTAT_DEVCONWUE (1 << 15)
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#define USBH_ROOTSTAT_OVRCURI (1 << 1)
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#define USBH_ROOTSTAT_LOCPWRS (1 << 0)
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#define USBH_PORTSTAT(x) (0xf4 + ((x) * 4))
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#define USBH_PORTSTAT_PRTRSTSC (1 << 20)
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#define USBH_PORTSTAT_OVRCURIC (1 << 19)
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#define USBH_PORTSTAT_PRTSTATSC (1 << 18)
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#define USBH_PORTSTAT_PRTENBLSC (1 << 17)
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#define USBH_PORTSTAT_CONNECTSC (1 << 16)
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#define USBH_PORTSTAT_LSDEVCON (1 << 9)
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#define USBH_PORTSTAT_PRTPWRST (1 << 8)
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#define USBH_PORTSTAT_PRTRSTST (1 << 4)
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#define USBH_PORTSTAT_PRTOVRCURI (1 << 3)
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#define USBH_PORTSTAT_PRTSUSPST (1 << 2)
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#define USBH_PORTSTAT_PRTENABST (1 << 1)
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#define USBH_PORTSTAT_CURCONST (1 << 0)
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#define USB_DMAREV 0x800
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#define USB_DMAINTSTAT 0x804
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#define USB_DMAINTSTAT_EPERR (1 << 1)
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#define USB_DMAINTSTAT_ETDERR (1 << 0)
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#define USB_DMAINTEN 0x808
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#define USB_DMAINTEN_EPERRINTEN (1 << 1)
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#define USB_DMAINTEN_ETDERRINTEN (1 << 0)
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#define USB_ETDDMAERSTAT 0x80c
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#define USB_EPDMAERSTAT 0x810
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#define USB_ETDDMAEN 0x820
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#define USB_EPDMAEN 0x824
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#define USB_ETDDMAXTEN 0x828
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#define USB_EPDMAXTEN 0x82c
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#define USB_ETDDMAENXYT 0x830
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#define USB_EPDMAENXYT 0x834
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#define USB_ETDDMABST4EN 0x838
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#define USB_EPDMABST4EN 0x83c
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#define USB_MISCCONTROL 0x840
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#define USB_MISCCONTROL_ISOPREVFRM (1 << 3)
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#define USB_MISCCONTROL_SKPRTRY (1 << 2)
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#define USB_MISCCONTROL_ARBMODE (1 << 1)
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#define USB_MISCCONTROL_FILTCC (1 << 0)
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#define USB_ETDDMACHANLCLR 0x848
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#define USB_EPDMACHANLCLR 0x84c
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#define USB_ETDSMSA(x) (0x900 + ((x) * 4))
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#define USB_EPSMSA(x) (0x980 + ((x) * 4))
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#define USB_ETDDMABUFPTR(x) (0xa00 + ((x) * 4))
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#define USB_EPDMABUFPTR(x) (0xa80 + ((x) * 4))
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#define USB_ETD_DWORD(x, w) (0x200 + ((x) * 16) + ((w) * 4))
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#define DW0_ADDRESS 0
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#define DW0_ENDPNT 7
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#define DW0_DIRECT 11
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#define DW0_SPEED 13
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#define DW0_FORMAT 14
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#define DW0_MAXPKTSIZ 16
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#define DW0_HALTED 27
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#define DW0_TOGCRY 28
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#define DW0_SNDNAK 30
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#define DW1_XBUFSRTAD 0
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#define DW1_YBUFSRTAD 16
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#define DW2_RTRYDELAY 0
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#define DW2_POLINTERV 0
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#define DW2_STARTFRM 0
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#define DW2_RELPOLPOS 8
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#define DW2_DIRPID 16
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#define DW2_BUFROUND 18
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#define DW2_DELAYINT 19
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#define DW2_DATATOG 22
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#define DW2_ERRORCNT 24
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#define DW2_COMPCODE 28
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#define DW3_TOTBYECNT 0
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#define DW3_PKTLEN0 0
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#define DW3_COMPCODE0 12
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#define DW3_PKTLEN1 16
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#define DW3_BUFSIZE 21
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#define DW3_COMPCODE1 28
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#define USBCTRL 0x600
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#define USBCTRL_I2C_WU_INT_STAT (1 << 27)
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#define USBCTRL_OTG_WU_INT_STAT (1 << 26)
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#define USBCTRL_HOST_WU_INT_STAT (1 << 25)
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#define USBCTRL_FNT_WU_INT_STAT (1 << 24)
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#define USBCTRL_I2C_WU_INT_EN (1 << 19)
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#define USBCTRL_OTG_WU_INT_EN (1 << 18)
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#define USBCTRL_HOST_WU_INT_EN (1 << 17)
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#define USBCTRL_FNT_WU_INT_EN (1 << 16)
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#define USBCTRL_OTC_RCV_RXDP (1 << 13)
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#define USBCTRL_HOST1_BYP_TLL (1 << 12)
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#define USBCTRL_OTG_BYP_VAL(x) ((x) << 10)
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#define USBCTRL_HOST1_BYP_VAL(x) ((x) << 8)
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#define USBCTRL_OTG_PWR_MASK (1 << 6)
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#define USBCTRL_HOST1_PWR_MASK (1 << 5)
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#define USBCTRL_HOST2_PWR_MASK (1 << 4)
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#define USBCTRL_USB_BYP (1 << 2)
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#define USBCTRL_HOST1_TXEN_OE (1 << 1)
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/* Values in TD blocks */
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#define TD_DIR_SETUP 0
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#define TD_DIR_OUT 1
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#define TD_DIR_IN 2
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#define TD_FORMAT_CONTROL 0
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#define TD_FORMAT_ISO 1
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#define TD_FORMAT_BULK 2
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#define TD_FORMAT_INT 3
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#define TD_TOGGLE_CARRY 0
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#define TD_TOGGLE_DATA0 2
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#define TD_TOGGLE_DATA1 3
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/* control transfer states */
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#define US_CTRL_SETUP 2
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#define US_CTRL_DATA 1
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#define US_CTRL_ACK 0
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/* bulk transfer main state and 0-length packet */
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#define US_BULK 1
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#define US_BULK0 0
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/*ETD format description*/
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#define IMX_FMT_CTRL 0x0
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#define IMX_FMT_ISO 0x1
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#define IMX_FMT_BULK 0x2
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#define IMX_FMT_INT 0x3
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static char fmt_urb_to_etd[4] = {
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/*PIPE_ISOCHRONOUS*/ IMX_FMT_ISO,
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/*PIPE_INTERRUPT*/ IMX_FMT_INT,
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/*PIPE_CONTROL*/ IMX_FMT_CTRL,
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/*PIPE_BULK*/ IMX_FMT_BULK
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};
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/* condition (error) CC codes and mapping (OHCI like) */
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#define TD_CC_NOERROR 0x00
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#define TD_CC_CRC 0x01
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#define TD_CC_BITSTUFFING 0x02
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#define TD_CC_DATATOGGLEM 0x03
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#define TD_CC_STALL 0x04
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#define TD_DEVNOTRESP 0x05
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#define TD_PIDCHECKFAIL 0x06
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/*#define TD_UNEXPECTEDPID 0x07 - reserved, not active on MX2*/
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#define TD_DATAOVERRUN 0x08
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#define TD_DATAUNDERRUN 0x09
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#define TD_BUFFEROVERRUN 0x0C
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#define TD_BUFFERUNDERRUN 0x0D
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#define TD_SCHEDULEOVERRUN 0x0E
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#define TD_NOTACCESSED 0x0F
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static const int cc_to_error[16] = {
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/* No Error */ 0,
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/* CRC Error */ -EILSEQ,
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/* Bit Stuff */ -EPROTO,
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/* Data Togg */ -EILSEQ,
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/* Stall */ -EPIPE,
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/* DevNotResp */ -ETIMEDOUT,
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/* PIDCheck */ -EPROTO,
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/* UnExpPID */ -EPROTO,
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/* DataOver */ -EOVERFLOW,
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/* DataUnder */ -EREMOTEIO,
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/* (for hw) */ -EIO,
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/* (for hw) */ -EIO,
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/* BufferOver */ -ECOMM,
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/* BuffUnder */ -ENOSR,
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/* (for HCD) */ -ENOSPC,
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/* (for HCD) */ -EALREADY
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};
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/* HCD data associated with a usb core URB */
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struct urb_priv {
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struct urb *urb;
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struct usb_host_endpoint *ep;
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int active;
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int state;
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struct td *isoc_td;
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int isoc_remaining;
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int isoc_status;
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};
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/* HCD data associated with a usb core endpoint */
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struct ep_priv {
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struct usb_host_endpoint *ep;
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struct list_head td_list;
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struct list_head queue;
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int etd[NUM_ISO_ETDS];
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int waiting_etd;
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};
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/* isoc packet */
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struct td {
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struct list_head list;
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struct urb *urb;
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struct usb_host_endpoint *ep;
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dma_addr_t data;
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unsigned long buf_addr;
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int len;
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int frame;
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int isoc_index;
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};
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/* HCD data associated with a hardware ETD */
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struct etd_priv {
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struct usb_host_endpoint *ep;
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struct urb *urb;
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struct td *td;
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struct list_head queue;
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dma_addr_t dma_handle;
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int alloc;
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int len;
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int dmem_size;
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int dmem_offset;
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int active_count;
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#ifdef DEBUG
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int activated_frame;
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int disactivated_frame;
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int last_int_frame;
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int last_req_frame;
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u32 submitted_dwords[4];
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#endif
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};
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/* Hardware data memory info */
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struct imx21_dmem_area {
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struct usb_host_endpoint *ep;
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unsigned int offset;
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unsigned int size;
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struct list_head list;
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};
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#ifdef DEBUG
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struct debug_usage_stats {
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unsigned int value;
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unsigned int maximum;
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};
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struct debug_stats {
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unsigned long submitted;
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unsigned long completed_ok;
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unsigned long completed_failed;
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unsigned long unlinked;
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unsigned long queue_etd;
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unsigned long queue_dmem;
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};
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struct debug_isoc_trace {
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int schedule_frame;
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int submit_frame;
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int request_len;
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int done_frame;
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int done_len;
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int cc;
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struct td *td;
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};
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#endif
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/* HCD data structure */
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struct imx21 {
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spinlock_t lock;
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struct device *dev;
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struct mx21_usbh_platform_data *pdata;
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struct list_head dmem_list;
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struct list_head queue_for_etd; /* eps queued due to etd shortage */
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struct list_head queue_for_dmem; /* etds queued due to dmem shortage */
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struct etd_priv etd[USB_NUM_ETD];
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struct clk *clk;
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void __iomem *regs;
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#ifdef DEBUG
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struct dentry *debug_root;
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struct debug_stats nonisoc_stats;
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struct debug_stats isoc_stats;
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struct debug_usage_stats etd_usage;
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struct debug_usage_stats dmem_usage;
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struct debug_isoc_trace isoc_trace[20];
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struct debug_isoc_trace isoc_trace_failed[20];
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unsigned long debug_unblocks;
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int isoc_trace_index;
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int isoc_trace_index_failed;
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#endif
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};
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#endif
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