35 lines
875 B
C
35 lines
875 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#ifndef __CXL_PCI_H__
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#define __CXL_PCI_H__
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#define CXL_MEMORY_PROGIF 0x10
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/*
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* See section 8.1 Configuration Space Registers in the CXL 2.0
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* Specification
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*/
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#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
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#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
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#define PCI_DVSEC_ID_CXL 0x0
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#define PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID 0x8
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#define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET 0xC
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/* BAR Indicator Register (BIR) */
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#define CXL_REGLOC_BIR_MASK GENMASK(2, 0)
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/* Register Block Identifier (RBI) */
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enum cxl_regloc_type {
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CXL_REGLOC_RBI_EMPTY = 0,
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CXL_REGLOC_RBI_COMPONENT,
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CXL_REGLOC_RBI_VIRT,
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CXL_REGLOC_RBI_MEMDEV,
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CXL_REGLOC_RBI_TYPES
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};
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#define CXL_REGLOC_RBI_MASK GENMASK(15, 8)
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#define CXL_REGLOC_ADDR_MASK GENMASK(31, 16)
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#endif /* __CXL_PCI_H__ */
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