159 lines
4.7 KiB
C
159 lines
4.7 KiB
C
#ifndef __BFIN_ENTRY_H
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#define __BFIN_ENTRY_H
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#include <asm/setup.h>
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#include <asm/page.h>
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#ifdef __ASSEMBLY__
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#define LFLUSH_I_AND_D 0x00000808
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#define LSIGTRAP 5
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/* process bits for task_struct.flags */
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#define PF_TRACESYS_OFF 3
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#define PF_TRACESYS_BIT 5
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#define PF_PTRACED_OFF 3
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#define PF_PTRACED_BIT 4
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#define PF_DTRACE_OFF 1
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#define PF_DTRACE_BIT 5
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/*
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* NOTE! The single-stepping code assumes that all interrupt handlers
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* start by saving SYSCFG on the stack with their first instruction.
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*/
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/* This one is used for exceptions, emulation, and NMI. It doesn't push
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RETI and doesn't do cli. */
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#define SAVE_ALL_SYS save_context_no_interrupts
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/* This is used for all normal interrupts. It saves a minimum of registers
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to the stack, loads the IRQ number, and jumps to common code. */
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#ifdef CONFIG_IPIPE
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# define LOAD_IPIPE_IPEND \
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P0.l = lo(IPEND); \
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P0.h = hi(IPEND); \
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R1 = [P0];
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#else
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# define LOAD_IPIPE_IPEND
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#endif
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#ifndef CONFIG_EXACT_HWERR
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/* As a debugging aid - we save IPEND when DEBUG_KERNEL is on,
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* otherwise it is a waste of cycles.
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*/
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# ifndef CONFIG_DEBUG_KERNEL
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#define INTERRUPT_ENTRY(N) \
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[--sp] = SYSCFG; \
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[--sp] = P0; /*orig_p0*/ \
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[--sp] = R0; /*orig_r0*/ \
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[--sp] = (R7:0,P5:0); \
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R0 = (N); \
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LOAD_IPIPE_IPEND \
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jump __common_int_entry;
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# else /* CONFIG_DEBUG_KERNEL */
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#define INTERRUPT_ENTRY(N) \
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[--sp] = SYSCFG; \
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[--sp] = P0; /*orig_p0*/ \
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[--sp] = R0; /*orig_r0*/ \
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[--sp] = (R7:0,P5:0); \
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p0.l = lo(IPEND); \
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p0.h = hi(IPEND); \
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r1 = [p0]; \
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R0 = (N); \
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LOAD_IPIPE_IPEND \
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jump __common_int_entry;
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# endif /* CONFIG_DEBUG_KERNEL */
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/* For timer interrupts, we need to save IPEND, since the user_mode
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*macro accesses it to determine where to account time.
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*/
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#define TIMER_INTERRUPT_ENTRY(N) \
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[--sp] = SYSCFG; \
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[--sp] = P0; /*orig_p0*/ \
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[--sp] = R0; /*orig_r0*/ \
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[--sp] = (R7:0,P5:0); \
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p0.l = lo(IPEND); \
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p0.h = hi(IPEND); \
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r1 = [p0]; \
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R0 = (N); \
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jump __common_int_entry;
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#else /* CONFIG_EXACT_HWERR is defined */
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/* if we want hardware error to be exact, we need to do a SSYNC (which forces
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* read/writes to complete to the memory controllers), and check to see that
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* caused a pending HW error condition. If so, we assume it was caused by user
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* space, by setting the same interrupt that we are in (so it goes off again)
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* and context restore, and a RTI (without servicing anything). This should
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* cause the pending HWERR to fire, and when that is done, this interrupt will
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* be re-serviced properly.
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* As you can see by the code - we actually need to do two SSYNCS - one to
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* make sure the read/writes complete, and another to make sure the hardware
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* error is recognized by the core.
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*/
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#define INTERRUPT_ENTRY(N) \
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SSYNC; \
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SSYNC; \
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[--sp] = SYSCFG; \
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[--sp] = P0; /*orig_p0*/ \
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[--sp] = R0; /*orig_r0*/ \
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[--sp] = (R7:0,P5:0); \
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R1 = ASTAT; \
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P0.L = LO(ILAT); \
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P0.H = HI(ILAT); \
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R0 = [P0]; \
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CC = BITTST(R0, EVT_IVHW_P); \
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IF CC JUMP 1f; \
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ASTAT = R1; \
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p0.l = lo(IPEND); \
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p0.h = hi(IPEND); \
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r1 = [p0]; \
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R0 = (N); \
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LOAD_IPIPE_IPEND \
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jump __common_int_entry; \
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1: ASTAT = R1; \
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RAISE N; \
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(R7:0, P5:0) = [SP++]; \
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SP += 0x8; \
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SYSCFG = [SP++]; \
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CSYNC; \
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RTI;
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#define TIMER_INTERRUPT_ENTRY(N) \
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SSYNC; \
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SSYNC; \
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[--sp] = SYSCFG; \
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[--sp] = P0; /*orig_p0*/ \
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[--sp] = R0; /*orig_r0*/ \
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[--sp] = (R7:0,P5:0); \
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R1 = ASTAT; \
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P0.L = LO(ILAT); \
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P0.H = HI(ILAT); \
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R0 = [P0]; \
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CC = BITTST(R0, EVT_IVHW_P); \
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IF CC JUMP 1f; \
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ASTAT = R1; \
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p0.l = lo(IPEND); \
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p0.h = hi(IPEND); \
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r1 = [p0]; \
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R0 = (N); \
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jump __common_int_entry; \
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1: ASTAT = R1; \
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RAISE N; \
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(R7:0, P5:0) = [SP++]; \
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SP += 0x8; \
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SYSCFG = [SP++]; \
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CSYNC; \
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RTI;
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#endif /* CONFIG_EXACT_HWERR */
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/* This one pushes RETI without using CLI. Interrupts are enabled. */
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#define SAVE_CONTEXT_SYSCALL save_context_syscall
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#define SAVE_CONTEXT save_context_with_interrupts
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#define SAVE_CONTEXT_CPLB save_context_cplb
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#define RESTORE_ALL_SYS restore_context_no_interrupts
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#define RESTORE_CONTEXT restore_context_with_interrupts
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#define RESTORE_CONTEXT_CPLB restore_context_cplb
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#endif /* __ASSEMBLY__ */
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#endif /* __BFIN_ENTRY_H */
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