406 lines
9.9 KiB
C
406 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets
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//
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// Copyright (c) 2019 HiSilicon Technologies Co., Ltd.
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// Author: John Garry <john.garry@huawei.com>
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#include <linux/acpi.h>
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#include <linux/bitops.h>
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#include <linux/dmi.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#define HISI_SFC_V3XX_VERSION (0x1f8)
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#define HISI_SFC_V3XX_INT_STAT (0x120)
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#define HISI_SFC_V3XX_INT_STAT_PP_ERR BIT(2)
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#define HISI_SFC_V3XX_INT_STAT_ADDR_IACCES BIT(5)
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#define HISI_SFC_V3XX_INT_CLR (0x12c)
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#define HISI_SFC_V3XX_INT_CLR_CLEAR (0xff)
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#define HISI_SFC_V3XX_CMD_CFG (0x300)
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#define HISI_SFC_V3XX_CMD_CFG_DUAL_IN_DUAL_OUT (1 << 17)
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#define HISI_SFC_V3XX_CMD_CFG_DUAL_IO (2 << 17)
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#define HISI_SFC_V3XX_CMD_CFG_FULL_DIO (3 << 17)
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#define HISI_SFC_V3XX_CMD_CFG_QUAD_IN_QUAD_OUT (5 << 17)
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#define HISI_SFC_V3XX_CMD_CFG_QUAD_IO (6 << 17)
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#define HISI_SFC_V3XX_CMD_CFG_FULL_QIO (7 << 17)
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#define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9
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#define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8)
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#define HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK BIT(7)
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#define HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF 4
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#define HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK BIT(3)
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#define HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF 1
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#define HISI_SFC_V3XX_CMD_CFG_START_MSK BIT(0)
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#define HISI_SFC_V3XX_CMD_INS (0x308)
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#define HISI_SFC_V3XX_CMD_ADDR (0x30c)
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#define HISI_SFC_V3XX_CMD_DATABUF0 (0x400)
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struct hisi_sfc_v3xx_host {
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struct device *dev;
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void __iomem *regbase;
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int max_cmd_dword;
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};
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#define HISI_SFC_V3XX_WAIT_TIMEOUT_US 1000000
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#define HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US 10
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static int hisi_sfc_v3xx_wait_cmd_idle(struct hisi_sfc_v3xx_host *host)
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{
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u32 reg;
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return readl_poll_timeout(host->regbase + HISI_SFC_V3XX_CMD_CFG, reg,
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!(reg & HISI_SFC_V3XX_CMD_CFG_START_MSK),
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HISI_SFC_V3XX_WAIT_POLL_INTERVAL_US,
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HISI_SFC_V3XX_WAIT_TIMEOUT_US);
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}
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static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem,
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struct spi_mem_op *op)
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{
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struct spi_device *spi = mem->spi;
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struct hisi_sfc_v3xx_host *host;
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uintptr_t addr = (uintptr_t)op->data.buf.in;
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int max_byte_count;
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host = spi_controller_get_devdata(spi->master);
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max_byte_count = host->max_cmd_dword * 4;
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if (!IS_ALIGNED(addr, 4) && op->data.nbytes >= 4)
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op->data.nbytes = 4 - (addr % 4);
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else if (op->data.nbytes > max_byte_count)
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op->data.nbytes = max_byte_count;
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return 0;
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}
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/*
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* memcpy_{to,from}io doesn't gurantee 32b accesses - which we require for the
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* DATABUF registers -so use __io{read,write}32_copy when possible. For
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* trailing bytes, copy them byte-by-byte from the DATABUF register, as we
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* can't clobber outside the source/dest buffer.
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*
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* For efficient data read/write, we try to put any start 32b unaligned data
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* into a separate transaction in hisi_sfc_v3xx_adjust_op_size().
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*/
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static void hisi_sfc_v3xx_read_databuf(struct hisi_sfc_v3xx_host *host,
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u8 *to, unsigned int len)
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{
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void __iomem *from;
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int i;
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from = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
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if (IS_ALIGNED((uintptr_t)to, 4)) {
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int words = len / 4;
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__ioread32_copy(to, from, words);
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len -= words * 4;
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if (len) {
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u32 val;
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to += words * 4;
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from += words * 4;
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val = __raw_readl(from);
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for (i = 0; i < len; i++, val >>= 8, to++)
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*to = (u8)val;
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}
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} else {
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for (i = 0; i < DIV_ROUND_UP(len, 4); i++, from += 4) {
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u32 val = __raw_readl(from);
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int j;
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for (j = 0; j < 4 && (j + (i * 4) < len);
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to++, val >>= 8, j++)
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*to = (u8)val;
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}
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}
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}
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static void hisi_sfc_v3xx_write_databuf(struct hisi_sfc_v3xx_host *host,
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const u8 *from, unsigned int len)
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{
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void __iomem *to;
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int i;
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to = host->regbase + HISI_SFC_V3XX_CMD_DATABUF0;
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if (IS_ALIGNED((uintptr_t)from, 4)) {
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int words = len / 4;
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__iowrite32_copy(to, from, words);
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len -= words * 4;
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if (len) {
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u32 val = 0;
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to += words * 4;
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from += words * 4;
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for (i = 0; i < len; i++, from++)
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val |= *from << i * 8;
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__raw_writel(val, to);
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}
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} else {
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for (i = 0; i < DIV_ROUND_UP(len, 4); i++, to += 4) {
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u32 val = 0;
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int j;
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for (j = 0; j < 4 && (j + (i * 4) < len);
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from++, j++)
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val |= *from << j * 8;
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__raw_writel(val, to);
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}
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}
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}
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static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host,
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const struct spi_mem_op *op,
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u8 chip_select)
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{
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int ret, len = op->data.nbytes;
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u32 int_stat, config = 0;
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if (op->addr.nbytes)
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config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK;
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switch (op->data.buswidth) {
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case 0 ... 1:
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break;
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case 2:
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if (op->addr.buswidth <= 1) {
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config |= HISI_SFC_V3XX_CMD_CFG_DUAL_IN_DUAL_OUT;
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} else if (op->addr.buswidth == 2) {
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if (op->cmd.buswidth <= 1) {
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config |= HISI_SFC_V3XX_CMD_CFG_DUAL_IO;
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} else if (op->cmd.buswidth == 2) {
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config |= HISI_SFC_V3XX_CMD_CFG_FULL_DIO;
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} else {
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return -EIO;
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}
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} else {
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return -EIO;
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}
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break;
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case 4:
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if (op->addr.buswidth <= 1) {
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config |= HISI_SFC_V3XX_CMD_CFG_QUAD_IN_QUAD_OUT;
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} else if (op->addr.buswidth == 4) {
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if (op->cmd.buswidth <= 1) {
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config |= HISI_SFC_V3XX_CMD_CFG_QUAD_IO;
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} else if (op->cmd.buswidth == 4) {
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config |= HISI_SFC_V3XX_CMD_CFG_FULL_QIO;
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} else {
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return -EIO;
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}
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} else {
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return -EIO;
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}
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break;
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default:
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return -EOPNOTSUPP;
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}
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if (op->data.dir != SPI_MEM_NO_DATA) {
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config |= (len - 1) << HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF;
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config |= HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK;
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}
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if (op->data.dir == SPI_MEM_DATA_OUT)
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hisi_sfc_v3xx_write_databuf(host, op->data.buf.out, len);
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else if (op->data.dir == SPI_MEM_DATA_IN)
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config |= HISI_SFC_V3XX_CMD_CFG_RW_MSK;
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config |= op->dummy.nbytes << HISI_SFC_V3XX_CMD_CFG_DUMMY_CNT_OFF |
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chip_select << HISI_SFC_V3XX_CMD_CFG_CS_SEL_OFF |
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HISI_SFC_V3XX_CMD_CFG_START_MSK;
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writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR);
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writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS);
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writel(config, host->regbase + HISI_SFC_V3XX_CMD_CFG);
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ret = hisi_sfc_v3xx_wait_cmd_idle(host);
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if (ret)
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return ret;
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/*
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* The interrupt status register indicates whether an error occurs
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* after per operation. Check it, and clear the interrupts for
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* next time judgement.
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*/
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int_stat = readl(host->regbase + HISI_SFC_V3XX_INT_STAT);
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writel(HISI_SFC_V3XX_INT_CLR_CLEAR,
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host->regbase + HISI_SFC_V3XX_INT_CLR);
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if (int_stat & HISI_SFC_V3XX_INT_STAT_ADDR_IACCES) {
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dev_err(host->dev, "fail to access protected address\n");
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return -EIO;
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}
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if (int_stat & HISI_SFC_V3XX_INT_STAT_PP_ERR) {
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dev_err(host->dev, "page program operation failed\n");
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return -EIO;
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}
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if (op->data.dir == SPI_MEM_DATA_IN)
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hisi_sfc_v3xx_read_databuf(host, op->data.buf.in, len);
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return 0;
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}
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static int hisi_sfc_v3xx_exec_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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struct hisi_sfc_v3xx_host *host;
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struct spi_device *spi = mem->spi;
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u8 chip_select = spi->chip_select;
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host = spi_controller_get_devdata(spi->master);
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return hisi_sfc_v3xx_generic_exec_op(host, op, chip_select);
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}
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static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = {
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.adjust_op_size = hisi_sfc_v3xx_adjust_op_size,
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.exec_op = hisi_sfc_v3xx_exec_op,
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};
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static int hisi_sfc_v3xx_buswidth_override_bits;
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/*
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* ACPI FW does not allow us to currently set the device buswidth, so quirk it
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* depending on the board.
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*/
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static int __init hisi_sfc_v3xx_dmi_quirk(const struct dmi_system_id *d)
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{
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hisi_sfc_v3xx_buswidth_override_bits = SPI_RX_QUAD | SPI_TX_QUAD;
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return 0;
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}
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static const struct dmi_system_id hisi_sfc_v3xx_dmi_quirk_table[] = {
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{
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.callback = hisi_sfc_v3xx_dmi_quirk,
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
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DMI_MATCH(DMI_PRODUCT_NAME, "D06"),
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},
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},
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{
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.callback = hisi_sfc_v3xx_dmi_quirk,
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
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DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 2280 V2"),
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},
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},
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{
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.callback = hisi_sfc_v3xx_dmi_quirk,
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Huawei"),
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DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 200 (Model 2280)"),
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},
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},
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{}
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};
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static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct hisi_sfc_v3xx_host *host;
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struct spi_controller *ctlr;
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u32 version;
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int ret;
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ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
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if (!ctlr)
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return -ENOMEM;
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ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
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SPI_TX_DUAL | SPI_TX_QUAD;
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ctlr->buswidth_override_bits = hisi_sfc_v3xx_buswidth_override_bits;
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host = spi_controller_get_devdata(ctlr);
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host->dev = dev;
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platform_set_drvdata(pdev, host);
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host->regbase = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(host->regbase)) {
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ret = PTR_ERR(host->regbase);
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goto err_put_master;
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}
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ctlr->bus_num = -1;
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ctlr->num_chipselect = 1;
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ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;
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version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
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switch (version) {
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case 0x351:
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host->max_cmd_dword = 64;
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break;
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default:
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host->max_cmd_dword = 16;
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break;
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}
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ret = devm_spi_register_controller(dev, ctlr);
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if (ret)
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goto err_put_master;
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dev_info(&pdev->dev, "hw version 0x%x\n", version);
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return 0;
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err_put_master:
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spi_master_put(ctlr);
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return ret;
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}
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#if IS_ENABLED(CONFIG_ACPI)
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static const struct acpi_device_id hisi_sfc_v3xx_acpi_ids[] = {
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{"HISI0341", 0},
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{}
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};
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MODULE_DEVICE_TABLE(acpi, hisi_sfc_v3xx_acpi_ids);
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#endif
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static struct platform_driver hisi_sfc_v3xx_spi_driver = {
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.driver = {
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.name = "hisi-sfc-v3xx",
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.acpi_match_table = ACPI_PTR(hisi_sfc_v3xx_acpi_ids),
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},
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.probe = hisi_sfc_v3xx_probe,
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};
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static int __init hisi_sfc_v3xx_spi_init(void)
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{
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dmi_check_system(hisi_sfc_v3xx_dmi_quirk_table);
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return platform_driver_register(&hisi_sfc_v3xx_spi_driver);
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}
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static void __exit hisi_sfc_v3xx_spi_exit(void)
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{
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platform_driver_unregister(&hisi_sfc_v3xx_spi_driver);
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}
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module_init(hisi_sfc_v3xx_spi_init);
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module_exit(hisi_sfc_v3xx_spi_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
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MODULE_DESCRIPTION("HiSilicon SPI NOR V3XX Flash Controller Driver for hi16xx chipsets");
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