542 lines
16 KiB
C
542 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Cadence MHDP DisplayPort SD0801 PHY driver.
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*
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* Copyright 2018 Cadence Design Systems, Inc.
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*
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#define DEFAULT_NUM_LANES 2
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#define MAX_NUM_LANES 4
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#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
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#define POLL_TIMEOUT_US 2000
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#define LANE_MASK 0x7
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/*
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* register offsets from DPTX PHY register block base (i.e MHDP
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* register base + 0x30a00)
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*/
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#define PHY_AUX_CONFIG 0x00
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#define PHY_AUX_CTRL 0x04
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#define PHY_RESET 0x20
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#define PHY_PMA_XCVR_PLLCLK_EN 0x24
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#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
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#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
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#define PHY_POWER_STATE_LN_0 0x0000
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#define PHY_POWER_STATE_LN_1 0x0008
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#define PHY_POWER_STATE_LN_2 0x0010
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#define PHY_POWER_STATE_LN_3 0x0018
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#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
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#define PHY_PMA_CMN_READY 0x34
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#define PHY_PMA_XCVR_TX_VMARGIN 0x38
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#define PHY_PMA_XCVR_TX_DEEMPH 0x3c
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/*
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* register offsets from SD0801 PHY register block base (i.e MHDP
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* register base + 0x500000)
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*/
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#define CMN_SSM_BANDGAP_TMR 0x00084
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#define CMN_SSM_BIAS_TMR 0x00088
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#define CMN_PLLSM0_PLLPRE_TMR 0x000a8
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#define CMN_PLLSM0_PLLLOCK_TMR 0x000b0
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#define CMN_PLLSM1_PLLPRE_TMR 0x000c8
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#define CMN_PLLSM1_PLLLOCK_TMR 0x000d0
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#define CMN_BGCAL_INIT_TMR 0x00190
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#define CMN_BGCAL_ITER_TMR 0x00194
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#define CMN_IBCAL_INIT_TMR 0x001d0
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#define CMN_PLL0_VCOCAL_INIT_TMR 0x00210
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#define CMN_PLL0_VCOCAL_ITER_TMR 0x00214
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#define CMN_PLL0_VCOCAL_REFTIM_START 0x00218
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#define CMN_PLL0_VCOCAL_PLLCNT_START 0x00220
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#define CMN_PLL0_INTDIV_M0 0x00240
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#define CMN_PLL0_FRACDIVL_M0 0x00244
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#define CMN_PLL0_FRACDIVH_M0 0x00248
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#define CMN_PLL0_HIGH_THR_M0 0x0024c
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#define CMN_PLL0_DSM_DIAG_M0 0x00250
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#define CMN_PLL0_LOCK_PLLCNT_START 0x00278
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#define CMN_PLL1_VCOCAL_INIT_TMR 0x00310
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#define CMN_PLL1_VCOCAL_ITER_TMR 0x00314
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#define CMN_PLL1_DSM_DIAG_M0 0x00350
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#define CMN_TXPUCAL_INIT_TMR 0x00410
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#define CMN_TXPUCAL_ITER_TMR 0x00414
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#define CMN_TXPDCAL_INIT_TMR 0x00430
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#define CMN_TXPDCAL_ITER_TMR 0x00434
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#define CMN_RXCAL_INIT_TMR 0x00450
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#define CMN_RXCAL_ITER_TMR 0x00454
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#define CMN_SD_CAL_INIT_TMR 0x00490
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#define CMN_SD_CAL_ITER_TMR 0x00494
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#define CMN_SD_CAL_REFTIM_START 0x00498
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#define CMN_SD_CAL_PLLCNT_START 0x004a0
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#define CMN_PDIAG_PLL0_CTRL_M0 0x00680
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#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x00684
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#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x00690
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#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x00694
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#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x00698
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#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x006d0
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#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x006d4
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#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x00704
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#define XCVR_DIAG_PLLDRC_CTRL 0x10394
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#define XCVR_DIAG_HSCLK_SEL 0x10398
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#define XCVR_DIAG_HSCLK_DIV 0x1039c
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#define TX_PSC_A0 0x10400
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#define TX_PSC_A1 0x10404
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#define TX_PSC_A2 0x10408
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#define TX_PSC_A3 0x1040c
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#define RX_PSC_A0 0x20000
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#define RX_PSC_A1 0x20004
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#define RX_PSC_A2 0x20008
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#define RX_PSC_A3 0x2000c
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#define PHY_PLL_CFG 0x30038
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struct cdns_dp_phy {
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void __iomem *base; /* DPTX registers base */
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void __iomem *sd_base; /* SD0801 registers base */
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u32 num_lanes; /* Number of lanes to use */
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u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
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struct device *dev;
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};
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static int cdns_dp_phy_init(struct phy *phy);
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static void cdns_dp_phy_run(struct cdns_dp_phy *cdns_phy);
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static void cdns_dp_phy_wait_pma_cmn_ready(struct cdns_dp_phy *cdns_phy);
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static void cdns_dp_phy_pma_cfg(struct cdns_dp_phy *cdns_phy);
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static void cdns_dp_phy_pma_cmn_cfg_25mhz(struct cdns_dp_phy *cdns_phy);
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static void cdns_dp_phy_pma_lane_cfg(struct cdns_dp_phy *cdns_phy,
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unsigned int lane);
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static void cdns_dp_phy_pma_cmn_vco_cfg_25mhz(struct cdns_dp_phy *cdns_phy);
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static void cdns_dp_phy_pma_cmn_rate(struct cdns_dp_phy *cdns_phy);
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static void cdns_dp_phy_write_field(struct cdns_dp_phy *cdns_phy,
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unsigned int offset,
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unsigned char start_bit,
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unsigned char num_bits,
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unsigned int val);
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static const struct phy_ops cdns_dp_phy_ops = {
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.init = cdns_dp_phy_init,
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.owner = THIS_MODULE,
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};
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static int cdns_dp_phy_init(struct phy *phy)
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{
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unsigned char lane_bits;
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struct cdns_dp_phy *cdns_phy = phy_get_drvdata(phy);
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writel(0x0003, cdns_phy->base + PHY_AUX_CTRL); /* enable AUX */
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/* PHY PMA registers configuration function */
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cdns_dp_phy_pma_cfg(cdns_phy);
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/*
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* Set lines power state to A0
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* Set lines pll clk enable to 0
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*/
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cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ,
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PHY_POWER_STATE_LN_0, 6, 0x0000);
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if (cdns_phy->num_lanes >= 2) {
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cdns_dp_phy_write_field(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ,
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PHY_POWER_STATE_LN_1, 6, 0x0000);
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if (cdns_phy->num_lanes == 4) {
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cdns_dp_phy_write_field(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ,
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PHY_POWER_STATE_LN_2, 6, 0);
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cdns_dp_phy_write_field(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ,
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PHY_POWER_STATE_LN_3, 6, 0);
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}
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}
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cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN,
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0, 1, 0x0000);
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if (cdns_phy->num_lanes >= 2) {
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cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN,
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1, 1, 0x0000);
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if (cdns_phy->num_lanes == 4) {
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cdns_dp_phy_write_field(cdns_phy,
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PHY_PMA_XCVR_PLLCLK_EN,
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2, 1, 0x0000);
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cdns_dp_phy_write_field(cdns_phy,
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PHY_PMA_XCVR_PLLCLK_EN,
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3, 1, 0x0000);
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}
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}
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/*
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* release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
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* used lanes
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*/
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lane_bits = (1 << cdns_phy->num_lanes) - 1;
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writel(((0xF & ~lane_bits) << 4) | (0xF & lane_bits),
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cdns_phy->base + PHY_RESET);
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/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
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writel(0x0001, cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN);
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/* PHY PMA registers configuration functions */
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cdns_dp_phy_pma_cmn_vco_cfg_25mhz(cdns_phy);
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cdns_dp_phy_pma_cmn_rate(cdns_phy);
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/* take out of reset */
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cdns_dp_phy_write_field(cdns_phy, PHY_RESET, 8, 1, 1);
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cdns_dp_phy_wait_pma_cmn_ready(cdns_phy);
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cdns_dp_phy_run(cdns_phy);
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return 0;
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}
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static void cdns_dp_phy_wait_pma_cmn_ready(struct cdns_dp_phy *cdns_phy)
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{
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unsigned int reg;
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int ret;
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ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_CMN_READY, reg,
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reg & 1, 0, 500);
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if (ret == -ETIMEDOUT)
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dev_err(cdns_phy->dev,
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"timeout waiting for PMA common ready\n");
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}
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static void cdns_dp_phy_pma_cfg(struct cdns_dp_phy *cdns_phy)
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{
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unsigned int i;
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/* PMA common configuration */
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cdns_dp_phy_pma_cmn_cfg_25mhz(cdns_phy);
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/* PMA lane configuration to deal with multi-link operation */
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for (i = 0; i < cdns_phy->num_lanes; i++)
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cdns_dp_phy_pma_lane_cfg(cdns_phy, i);
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}
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static void cdns_dp_phy_pma_cmn_cfg_25mhz(struct cdns_dp_phy *cdns_phy)
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{
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/* refclock registers - assumes 25 MHz refclock */
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writel(0x0019, cdns_phy->sd_base + CMN_SSM_BIAS_TMR);
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writel(0x0032, cdns_phy->sd_base + CMN_PLLSM0_PLLPRE_TMR);
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writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM0_PLLLOCK_TMR);
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writel(0x0032, cdns_phy->sd_base + CMN_PLLSM1_PLLPRE_TMR);
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writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM1_PLLLOCK_TMR);
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writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_INIT_TMR);
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writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_ITER_TMR);
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writel(0x0019, cdns_phy->sd_base + CMN_IBCAL_INIT_TMR);
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writel(0x001E, cdns_phy->sd_base + CMN_TXPUCAL_INIT_TMR);
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writel(0x0006, cdns_phy->sd_base + CMN_TXPUCAL_ITER_TMR);
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writel(0x001E, cdns_phy->sd_base + CMN_TXPDCAL_INIT_TMR);
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writel(0x0006, cdns_phy->sd_base + CMN_TXPDCAL_ITER_TMR);
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writel(0x02EE, cdns_phy->sd_base + CMN_RXCAL_INIT_TMR);
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writel(0x0006, cdns_phy->sd_base + CMN_RXCAL_ITER_TMR);
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writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_INIT_TMR);
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writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_ITER_TMR);
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writel(0x000E, cdns_phy->sd_base + CMN_SD_CAL_REFTIM_START);
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writel(0x012B, cdns_phy->sd_base + CMN_SD_CAL_PLLCNT_START);
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/* PLL registers */
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writel(0x0409, cdns_phy->sd_base + CMN_PDIAG_PLL0_CP_PADJ_M0);
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writel(0x1001, cdns_phy->sd_base + CMN_PDIAG_PLL0_CP_IADJ_M0);
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writel(0x0F08, cdns_phy->sd_base + CMN_PDIAG_PLL0_FILT_PADJ_M0);
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writel(0x0004, cdns_phy->sd_base + CMN_PLL0_DSM_DIAG_M0);
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writel(0x00FA, cdns_phy->sd_base + CMN_PLL0_VCOCAL_INIT_TMR);
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writel(0x0004, cdns_phy->sd_base + CMN_PLL0_VCOCAL_ITER_TMR);
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writel(0x00FA, cdns_phy->sd_base + CMN_PLL1_VCOCAL_INIT_TMR);
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writel(0x0004, cdns_phy->sd_base + CMN_PLL1_VCOCAL_ITER_TMR);
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writel(0x0318, cdns_phy->sd_base + CMN_PLL0_VCOCAL_REFTIM_START);
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}
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static void cdns_dp_phy_pma_cmn_vco_cfg_25mhz(struct cdns_dp_phy *cdns_phy)
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{
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/* Assumes 25 MHz refclock */
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switch (cdns_phy->max_bit_rate) {
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/* Setting VCO for 10.8GHz */
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case 2700:
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case 5400:
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writel(0x01B0, cdns_phy->sd_base + CMN_PLL0_INTDIV_M0);
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writel(0x0000, cdns_phy->sd_base + CMN_PLL0_FRACDIVL_M0);
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writel(0x0002, cdns_phy->sd_base + CMN_PLL0_FRACDIVH_M0);
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writel(0x0120, cdns_phy->sd_base + CMN_PLL0_HIGH_THR_M0);
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break;
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/* Setting VCO for 9.72GHz */
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case 2430:
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case 3240:
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writel(0x0184, cdns_phy->sd_base + CMN_PLL0_INTDIV_M0);
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writel(0xCCCD, cdns_phy->sd_base + CMN_PLL0_FRACDIVL_M0);
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writel(0x0002, cdns_phy->sd_base + CMN_PLL0_FRACDIVH_M0);
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writel(0x0104, cdns_phy->sd_base + CMN_PLL0_HIGH_THR_M0);
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break;
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/* Setting VCO for 8.64GHz */
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case 2160:
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case 4320:
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writel(0x0159, cdns_phy->sd_base + CMN_PLL0_INTDIV_M0);
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writel(0x999A, cdns_phy->sd_base + CMN_PLL0_FRACDIVL_M0);
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writel(0x0002, cdns_phy->sd_base + CMN_PLL0_FRACDIVH_M0);
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writel(0x00E7, cdns_phy->sd_base + CMN_PLL0_HIGH_THR_M0);
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break;
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/* Setting VCO for 8.1GHz */
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case 8100:
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writel(0x0144, cdns_phy->sd_base + CMN_PLL0_INTDIV_M0);
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writel(0x0000, cdns_phy->sd_base + CMN_PLL0_FRACDIVL_M0);
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writel(0x0002, cdns_phy->sd_base + CMN_PLL0_FRACDIVH_M0);
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writel(0x00D8, cdns_phy->sd_base + CMN_PLL0_HIGH_THR_M0);
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break;
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}
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writel(0x0002, cdns_phy->sd_base + CMN_PDIAG_PLL0_CTRL_M0);
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writel(0x0318, cdns_phy->sd_base + CMN_PLL0_VCOCAL_PLLCNT_START);
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}
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static void cdns_dp_phy_pma_cmn_rate(struct cdns_dp_phy *cdns_phy)
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{
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unsigned int clk_sel_val = 0;
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unsigned int hsclk_div_val = 0;
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unsigned int i;
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/* 16'h0000 for single DP link configuration */
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writel(0x0000, cdns_phy->sd_base + PHY_PLL_CFG);
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switch (cdns_phy->max_bit_rate) {
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case 1620:
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clk_sel_val = 0x0f01;
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hsclk_div_val = 2;
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break;
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case 2160:
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case 2430:
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case 2700:
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clk_sel_val = 0x0701;
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hsclk_div_val = 1;
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break;
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case 3240:
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clk_sel_val = 0x0b00;
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hsclk_div_val = 2;
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break;
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case 4320:
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case 5400:
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clk_sel_val = 0x0301;
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hsclk_div_val = 0;
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break;
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case 8100:
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clk_sel_val = 0x0200;
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hsclk_div_val = 0;
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break;
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}
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writel(clk_sel_val, cdns_phy->sd_base + CMN_PDIAG_PLL0_CLK_SEL_M0);
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/* PMA lane configuration to deal with multi-link operation */
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for (i = 0; i < cdns_phy->num_lanes; i++) {
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writel(hsclk_div_val,
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cdns_phy->sd_base + (XCVR_DIAG_HSCLK_DIV | (i<<11)));
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}
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}
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static void cdns_dp_phy_pma_lane_cfg(struct cdns_dp_phy *cdns_phy,
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unsigned int lane)
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{
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unsigned int lane_bits = (lane & LANE_MASK) << 11;
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/* Writing Tx/Rx Power State Controllers registers */
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writel(0x00FB, cdns_phy->sd_base + (TX_PSC_A0 | lane_bits));
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writel(0x04AA, cdns_phy->sd_base + (TX_PSC_A2 | lane_bits));
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writel(0x04AA, cdns_phy->sd_base + (TX_PSC_A3 | lane_bits));
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writel(0x0000, cdns_phy->sd_base + (RX_PSC_A0 | lane_bits));
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writel(0x0000, cdns_phy->sd_base + (RX_PSC_A2 | lane_bits));
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writel(0x0000, cdns_phy->sd_base + (RX_PSC_A3 | lane_bits));
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writel(0x0001, cdns_phy->sd_base + (XCVR_DIAG_PLLDRC_CTRL | lane_bits));
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writel(0x0000, cdns_phy->sd_base + (XCVR_DIAG_HSCLK_SEL | lane_bits));
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}
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static void cdns_dp_phy_run(struct cdns_dp_phy *cdns_phy)
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{
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unsigned int read_val;
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u32 write_val1 = 0;
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u32 write_val2 = 0;
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u32 mask = 0;
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int ret;
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/*
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* waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
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* master lane
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*/
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ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN_ACK,
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read_val, read_val & 1, 0, POLL_TIMEOUT_US);
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if (ret == -ETIMEDOUT)
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dev_err(cdns_phy->dev,
|
|
"timeout waiting for link PLL clock enable ack\n");
|
|
|
|
ndelay(100);
|
|
|
|
switch (cdns_phy->num_lanes) {
|
|
|
|
case 1: /* lane 0 */
|
|
write_val1 = 0x00000004;
|
|
write_val2 = 0x00000001;
|
|
mask = 0x0000003f;
|
|
break;
|
|
case 2: /* lane 0-1 */
|
|
write_val1 = 0x00000404;
|
|
write_val2 = 0x00000101;
|
|
mask = 0x00003f3f;
|
|
break;
|
|
case 4: /* lane 0-3 */
|
|
write_val1 = 0x04040404;
|
|
write_val2 = 0x01010101;
|
|
mask = 0x3f3f3f3f;
|
|
break;
|
|
}
|
|
|
|
writel(write_val1, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
|
|
|
|
ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK,
|
|
read_val, (read_val & mask) == write_val1, 0,
|
|
POLL_TIMEOUT_US);
|
|
if (ret == -ETIMEDOUT)
|
|
dev_err(cdns_phy->dev,
|
|
"timeout waiting for link power state ack\n");
|
|
|
|
writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
|
|
ndelay(100);
|
|
|
|
writel(write_val2, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
|
|
|
|
ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK,
|
|
read_val, (read_val & mask) == write_val2, 0,
|
|
POLL_TIMEOUT_US);
|
|
if (ret == -ETIMEDOUT)
|
|
dev_err(cdns_phy->dev,
|
|
"timeout waiting for link power state ack\n");
|
|
|
|
writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
|
|
ndelay(100);
|
|
}
|
|
|
|
static void cdns_dp_phy_write_field(struct cdns_dp_phy *cdns_phy,
|
|
unsigned int offset,
|
|
unsigned char start_bit,
|
|
unsigned char num_bits,
|
|
unsigned int val)
|
|
{
|
|
unsigned int read_val;
|
|
|
|
read_val = readl(cdns_phy->base + offset);
|
|
writel(((val << start_bit) | (read_val & ~(((1 << num_bits) - 1) <<
|
|
start_bit))), cdns_phy->base + offset);
|
|
}
|
|
|
|
static int cdns_dp_phy_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *regs;
|
|
struct cdns_dp_phy *cdns_phy;
|
|
struct device *dev = &pdev->dev;
|
|
struct phy_provider *phy_provider;
|
|
struct phy *phy;
|
|
int err;
|
|
|
|
cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
|
|
if (!cdns_phy)
|
|
return -ENOMEM;
|
|
|
|
cdns_phy->dev = &pdev->dev;
|
|
|
|
phy = devm_phy_create(dev, NULL, &cdns_dp_phy_ops);
|
|
if (IS_ERR(phy)) {
|
|
dev_err(dev, "failed to create DisplayPort PHY\n");
|
|
return PTR_ERR(phy);
|
|
}
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
cdns_phy->base = devm_ioremap_resource(&pdev->dev, regs);
|
|
if (IS_ERR(cdns_phy->base))
|
|
return PTR_ERR(cdns_phy->base);
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
cdns_phy->sd_base = devm_ioremap_resource(&pdev->dev, regs);
|
|
if (IS_ERR(cdns_phy->sd_base))
|
|
return PTR_ERR(cdns_phy->sd_base);
|
|
|
|
err = device_property_read_u32(dev, "num_lanes",
|
|
&(cdns_phy->num_lanes));
|
|
if (err)
|
|
cdns_phy->num_lanes = DEFAULT_NUM_LANES;
|
|
|
|
switch (cdns_phy->num_lanes) {
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
/* valid number of lanes */
|
|
break;
|
|
default:
|
|
dev_err(dev, "unsupported number of lanes: %d\n",
|
|
cdns_phy->num_lanes);
|
|
return -EINVAL;
|
|
}
|
|
|
|
err = device_property_read_u32(dev, "max_bit_rate",
|
|
&(cdns_phy->max_bit_rate));
|
|
if (err)
|
|
cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
|
|
|
|
switch (cdns_phy->max_bit_rate) {
|
|
case 2160:
|
|
case 2430:
|
|
case 2700:
|
|
case 3240:
|
|
case 4320:
|
|
case 5400:
|
|
case 8100:
|
|
/* valid bit rate */
|
|
break;
|
|
default:
|
|
dev_err(dev, "unsupported max bit rate: %dMbps\n",
|
|
cdns_phy->max_bit_rate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
phy_set_drvdata(phy, cdns_phy);
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
|
|
dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n",
|
|
cdns_phy->num_lanes,
|
|
cdns_phy->max_bit_rate / 1000,
|
|
cdns_phy->max_bit_rate % 1000);
|
|
|
|
return PTR_ERR_OR_ZERO(phy_provider);
|
|
}
|
|
|
|
static const struct of_device_id cdns_dp_phy_of_match[] = {
|
|
{
|
|
.compatible = "cdns,dp-phy"
|
|
},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, cdns_dp_phy_of_match);
|
|
|
|
static struct platform_driver cdns_dp_phy_driver = {
|
|
.probe = cdns_dp_phy_probe,
|
|
.driver = {
|
|
.name = "cdns-dp-phy",
|
|
.of_match_table = cdns_dp_phy_of_match,
|
|
}
|
|
};
|
|
module_platform_driver(cdns_dp_phy_driver);
|
|
|
|
MODULE_AUTHOR("Cadence Design Systems, Inc.");
|
|
MODULE_DESCRIPTION("Cadence MHDP PHY driver");
|
|
MODULE_LICENSE("GPL v2");
|