540 lines
15 KiB
C
540 lines
15 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions: *
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "i915_drv.h"
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#include "intel_engine.h"
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#include "intel_gt.h"
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#include "intel_lrc_reg.h"
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#include "intel_mocs.h"
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#include "intel_ring.h"
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/* structures required */
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struct drm_i915_mocs_entry {
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u32 control_value;
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u16 l3cc_value;
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u16 used;
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};
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struct drm_i915_mocs_table {
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unsigned int size;
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unsigned int n_entries;
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const struct drm_i915_mocs_entry *table;
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};
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/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
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#define _LE_CACHEABILITY(value) ((value) << 0)
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#define _LE_TGT_CACHE(value) ((value) << 2)
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#define LE_LRUM(value) ((value) << 4)
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#define LE_AOM(value) ((value) << 6)
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#define LE_RSC(value) ((value) << 7)
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#define LE_SCC(value) ((value) << 8)
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#define LE_PFM(value) ((value) << 11)
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#define LE_SCF(value) ((value) << 14)
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#define LE_COS(value) ((value) << 15)
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#define LE_SSE(value) ((value) << 17)
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/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
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#define L3_ESC(value) ((value) << 0)
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#define L3_SCC(value) ((value) << 1)
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#define _L3_CACHEABILITY(value) ((value) << 4)
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/* Helper defines */
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#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
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/* (e)LLC caching options */
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/*
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* Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
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* the same as LE_UC
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*/
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#define LE_0_PAGETABLE _LE_CACHEABILITY(0)
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#define LE_1_UC _LE_CACHEABILITY(1)
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#define LE_2_WT _LE_CACHEABILITY(2)
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#define LE_3_WB _LE_CACHEABILITY(3)
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/* Target cache */
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#define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0)
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#define LE_TC_1_LLC _LE_TGT_CACHE(1)
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#define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2)
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#define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3)
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/* L3 caching options */
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#define L3_0_DIRECT _L3_CACHEABILITY(0)
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#define L3_1_UC _L3_CACHEABILITY(1)
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#define L3_2_RESERVED _L3_CACHEABILITY(2)
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#define L3_3_WB _L3_CACHEABILITY(3)
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#define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
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[__idx] = { \
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.control_value = __control_value, \
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.l3cc_value = __l3cc_value, \
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.used = 1, \
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}
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/*
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* MOCS tables
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*
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* These are the MOCS tables that are programmed across all the rings.
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* The control value is programmed to all the rings that support the
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* MOCS registers. While the l3cc_values are only programmed to the
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* LNCFCMOCS0 - LNCFCMOCS32 registers.
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*
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* These tables are intended to be kept reasonably consistent across
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* HW platforms, and for ICL+, be identical across OSes. To achieve
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* that, for Icelake and above, list of entries is published as part
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* of bspec.
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*
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* Entries not part of the following tables are undefined as far as
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* userspace is concerned and shouldn't be relied upon. For Gen < 12
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* they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
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* PTE and will be initialized to an invalid value.
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*
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* The last few entries are reserved by the hardware. For ICL+ they
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* should be initialized according to bspec and never used, for older
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* platforms they should never be written to.
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*
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* NOTE: These tables are part of bspec and defined as part of hardware
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* interface for ICL+. For older platforms, they are part of kernel
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* ABI. It is expected that, for specific hardware platform, existing
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* entries will remain constant and the table will only be updated by
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* adding new entries, filling unused positions.
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*/
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#define GEN9_MOCS_ENTRIES \
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MOCS_ENTRY(I915_MOCS_UNCACHED, \
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LE_1_UC | LE_TC_2_LLC_ELLC, \
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L3_1_UC), \
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MOCS_ENTRY(I915_MOCS_PTE, \
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LE_0_PAGETABLE | LE_TC_0_PAGETABLE | LE_LRUM(3), \
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L3_3_WB)
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static const struct drm_i915_mocs_entry skl_mocs_table[] = {
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GEN9_MOCS_ENTRIES,
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MOCS_ENTRY(I915_MOCS_CACHED,
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LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
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L3_3_WB),
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/*
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* mocs:63
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* - used by the L3 for all of its evictions.
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* Thus it is expected to allow LLC cacheability to enable coherent
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* flows to be maintained.
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* - used to force L3 uncachable cycles.
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* Thus it is expected to make the surface L3 uncacheable.
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*/
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MOCS_ENTRY(63,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_1_UC)
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};
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/* NOTE: the LE_TGT_CACHE is not used on Broxton */
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static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
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GEN9_MOCS_ENTRIES,
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MOCS_ENTRY(I915_MOCS_CACHED,
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LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
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L3_3_WB)
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};
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#define GEN11_MOCS_ENTRIES \
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/* Entries 0 and 1 are defined per-platform */ \
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/* Base - L3 + LLC */ \
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MOCS_ENTRY(2, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
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L3_3_WB), \
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/* Base - Uncached */ \
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MOCS_ENTRY(3, \
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LE_1_UC | LE_TC_1_LLC, \
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L3_1_UC), \
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/* Base - L3 */ \
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MOCS_ENTRY(4, \
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LE_1_UC | LE_TC_1_LLC, \
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L3_3_WB), \
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/* Base - LLC */ \
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MOCS_ENTRY(5, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
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L3_1_UC), \
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/* Age 0 - LLC */ \
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MOCS_ENTRY(6, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
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L3_1_UC), \
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/* Age 0 - L3 + LLC */ \
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MOCS_ENTRY(7, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
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L3_3_WB), \
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/* Age: Don't Chg. - LLC */ \
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MOCS_ENTRY(8, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
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L3_1_UC), \
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/* Age: Don't Chg. - L3 + LLC */ \
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MOCS_ENTRY(9, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
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L3_3_WB), \
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/* No AOM - LLC */ \
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MOCS_ENTRY(10, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
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L3_1_UC), \
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/* No AOM - L3 + LLC */ \
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MOCS_ENTRY(11, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
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L3_3_WB), \
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/* No AOM; Age 0 - LLC */ \
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MOCS_ENTRY(12, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
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L3_1_UC), \
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/* No AOM; Age 0 - L3 + LLC */ \
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MOCS_ENTRY(13, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
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L3_3_WB), \
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/* No AOM; Age:DC - LLC */ \
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MOCS_ENTRY(14, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
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L3_1_UC), \
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/* No AOM; Age:DC - L3 + LLC */ \
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MOCS_ENTRY(15, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
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L3_3_WB), \
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/* Self-Snoop - L3 + LLC */ \
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MOCS_ENTRY(18, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
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L3_3_WB), \
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/* Skip Caching - L3 + LLC(12.5%) */ \
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MOCS_ENTRY(19, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \
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L3_3_WB), \
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/* Skip Caching - L3 + LLC(25%) */ \
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MOCS_ENTRY(20, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \
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L3_3_WB), \
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/* Skip Caching - L3 + LLC(50%) */ \
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MOCS_ENTRY(21, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \
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L3_3_WB), \
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/* Skip Caching - L3 + LLC(75%) */ \
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MOCS_ENTRY(22, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \
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L3_3_WB), \
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/* Skip Caching - L3 + LLC(87.5%) */ \
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MOCS_ENTRY(23, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
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L3_3_WB), \
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/* HW Reserved - SW program but never use */ \
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MOCS_ENTRY(62, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
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L3_1_UC), \
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/* HW Reserved - SW program but never use */ \
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MOCS_ENTRY(63, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
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L3_1_UC)
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static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
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/*
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* NOTE:
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* Reserved and unspecified MOCS indices have been set to (L3 + LCC).
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* These reserved entries should never be used, they may be changed
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* to low performant variants with better coherency in the future if
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* more entries are needed. We are programming index I915_MOCS_PTE(1)
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* only, __init_mocs_table() take care to program unused index with
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* this entry.
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*/
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MOCS_ENTRY(I915_MOCS_PTE,
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LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
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L3_1_UC),
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GEN11_MOCS_ENTRIES,
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/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
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MOCS_ENTRY(48,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_3_WB),
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/* Implicitly enable L1 - HDC:L1 + L3 */
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MOCS_ENTRY(49,
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LE_1_UC | LE_TC_1_LLC,
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L3_3_WB),
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/* Implicitly enable L1 - HDC:L1 + LLC */
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MOCS_ENTRY(50,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_1_UC),
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/* Implicitly enable L1 - HDC:L1 */
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MOCS_ENTRY(51,
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LE_1_UC | LE_TC_1_LLC,
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L3_1_UC),
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/* HW Special Case (CCS) */
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MOCS_ENTRY(60,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_1_UC),
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/* HW Special Case (Displayable) */
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MOCS_ENTRY(61,
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LE_1_UC | LE_TC_1_LLC,
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L3_3_WB),
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};
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static const struct drm_i915_mocs_entry icl_mocs_table[] = {
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/* Base - Uncached (Deprecated) */
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MOCS_ENTRY(I915_MOCS_UNCACHED,
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LE_1_UC | LE_TC_1_LLC,
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L3_1_UC),
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/* Base - L3 + LeCC:PAT (Deprecated) */
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MOCS_ENTRY(I915_MOCS_PTE,
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LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
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L3_3_WB),
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GEN11_MOCS_ENTRIES
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};
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static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
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/* Error */
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MOCS_ENTRY(0, 0, L3_0_DIRECT),
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/* UC */
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MOCS_ENTRY(1, 0, L3_1_UC),
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/* Reserved */
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MOCS_ENTRY(2, 0, L3_0_DIRECT),
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MOCS_ENTRY(3, 0, L3_0_DIRECT),
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MOCS_ENTRY(4, 0, L3_0_DIRECT),
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/* WB - L3 */
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MOCS_ENTRY(5, 0, L3_3_WB),
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/* WB - L3 50% */
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MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
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/* WB - L3 25% */
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MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
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/* WB - L3 12.5% */
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MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
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/* HDC:L1 + L3 */
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MOCS_ENTRY(48, 0, L3_3_WB),
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/* HDC:L1 */
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MOCS_ENTRY(49, 0, L3_1_UC),
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/* HW Reserved */
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MOCS_ENTRY(60, 0, L3_1_UC),
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MOCS_ENTRY(61, 0, L3_1_UC),
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MOCS_ENTRY(62, 0, L3_1_UC),
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MOCS_ENTRY(63, 0, L3_1_UC),
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};
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enum {
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HAS_GLOBAL_MOCS = BIT(0),
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HAS_ENGINE_MOCS = BIT(1),
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HAS_RENDER_L3CC = BIT(2),
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};
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static bool has_l3cc(const struct drm_i915_private *i915)
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{
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return true;
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}
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static bool has_global_mocs(const struct drm_i915_private *i915)
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{
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return HAS_GLOBAL_MOCS_REGISTERS(i915);
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}
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static bool has_mocs(const struct drm_i915_private *i915)
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{
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return !IS_DGFX(i915);
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}
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static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
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struct drm_i915_mocs_table *table)
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{
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unsigned int flags;
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if (IS_DG1(i915)) {
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table->size = ARRAY_SIZE(dg1_mocs_table);
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table->table = dg1_mocs_table;
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table->n_entries = GEN9_NUM_MOCS_ENTRIES;
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} else if (INTEL_GEN(i915) >= 12) {
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table->size = ARRAY_SIZE(tgl_mocs_table);
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table->table = tgl_mocs_table;
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table->n_entries = GEN9_NUM_MOCS_ENTRIES;
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} else if (IS_GEN(i915, 11)) {
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table->size = ARRAY_SIZE(icl_mocs_table);
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table->table = icl_mocs_table;
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table->n_entries = GEN9_NUM_MOCS_ENTRIES;
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} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
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table->size = ARRAY_SIZE(skl_mocs_table);
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table->n_entries = GEN9_NUM_MOCS_ENTRIES;
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table->table = skl_mocs_table;
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} else if (IS_GEN9_LP(i915)) {
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table->size = ARRAY_SIZE(broxton_mocs_table);
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table->n_entries = GEN9_NUM_MOCS_ENTRIES;
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table->table = broxton_mocs_table;
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} else {
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drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
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"Platform that should have a MOCS table does not.\n");
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return 0;
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}
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if (GEM_DEBUG_WARN_ON(table->size > table->n_entries))
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return 0;
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/* WaDisableSkipCaching:skl,bxt,kbl,glk */
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if (IS_GEN(i915, 9)) {
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int i;
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for (i = 0; i < table->size; i++)
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if (GEM_DEBUG_WARN_ON(table->table[i].l3cc_value &
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(L3_ESC(1) | L3_SCC(0x7))))
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return 0;
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}
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flags = 0;
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if (has_mocs(i915)) {
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if (has_global_mocs(i915))
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flags |= HAS_GLOBAL_MOCS;
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else
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flags |= HAS_ENGINE_MOCS;
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}
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if (has_l3cc(i915))
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flags |= HAS_RENDER_L3CC;
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return flags;
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}
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/*
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* Get control_value from MOCS entry taking into account when it's not used:
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* I915_MOCS_PTE's value is returned in this case.
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*/
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static u32 get_entry_control(const struct drm_i915_mocs_table *table,
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unsigned int index)
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{
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if (index < table->size && table->table[index].used)
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return table->table[index].control_value;
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return table->table[I915_MOCS_PTE].control_value;
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}
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#define for_each_mocs(mocs, t, i) \
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for (i = 0; \
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i < (t)->n_entries ? (mocs = get_entry_control((t), i)), 1 : 0;\
|
|
i++)
|
|
|
|
static void __init_mocs_table(struct intel_uncore *uncore,
|
|
const struct drm_i915_mocs_table *table,
|
|
u32 addr)
|
|
{
|
|
unsigned int i;
|
|
u32 mocs;
|
|
|
|
for_each_mocs(mocs, table, i)
|
|
intel_uncore_write_fw(uncore, _MMIO(addr + i * 4), mocs);
|
|
}
|
|
|
|
static u32 mocs_offset(const struct intel_engine_cs *engine)
|
|
{
|
|
static const u32 offset[] = {
|
|
[RCS0] = __GEN9_RCS0_MOCS0,
|
|
[VCS0] = __GEN9_VCS0_MOCS0,
|
|
[VCS1] = __GEN9_VCS1_MOCS0,
|
|
[VECS0] = __GEN9_VECS0_MOCS0,
|
|
[BCS0] = __GEN9_BCS0_MOCS0,
|
|
[VCS2] = __GEN11_VCS2_MOCS0,
|
|
};
|
|
|
|
GEM_BUG_ON(engine->id >= ARRAY_SIZE(offset));
|
|
return offset[engine->id];
|
|
}
|
|
|
|
static void init_mocs_table(struct intel_engine_cs *engine,
|
|
const struct drm_i915_mocs_table *table)
|
|
{
|
|
__init_mocs_table(engine->uncore, table, mocs_offset(engine));
|
|
}
|
|
|
|
/*
|
|
* Get l3cc_value from MOCS entry taking into account when it's not used:
|
|
* I915_MOCS_PTE's value is returned in this case.
|
|
*/
|
|
static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
|
|
unsigned int index)
|
|
{
|
|
if (index < table->size && table->table[index].used)
|
|
return table->table[index].l3cc_value;
|
|
|
|
return table->table[I915_MOCS_PTE].l3cc_value;
|
|
}
|
|
|
|
static u32 l3cc_combine(u16 low, u16 high)
|
|
{
|
|
return low | (u32)high << 16;
|
|
}
|
|
|
|
#define for_each_l3cc(l3cc, t, i) \
|
|
for (i = 0; \
|
|
i < ((t)->n_entries + 1) / 2 ? \
|
|
(l3cc = l3cc_combine(get_entry_l3cc((t), 2 * i), \
|
|
get_entry_l3cc((t), 2 * i + 1))), 1 : \
|
|
0; \
|
|
i++)
|
|
|
|
static void init_l3cc_table(struct intel_engine_cs *engine,
|
|
const struct drm_i915_mocs_table *table)
|
|
{
|
|
struct intel_uncore *uncore = engine->uncore;
|
|
unsigned int i;
|
|
u32 l3cc;
|
|
|
|
for_each_l3cc(l3cc, table, i)
|
|
intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
|
|
}
|
|
|
|
void intel_mocs_init_engine(struct intel_engine_cs *engine)
|
|
{
|
|
struct drm_i915_mocs_table table;
|
|
unsigned int flags;
|
|
|
|
/* Called under a blanket forcewake */
|
|
assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
|
|
|
|
flags = get_mocs_settings(engine->i915, &table);
|
|
if (!flags)
|
|
return;
|
|
|
|
/* Platforms with global MOCS do not need per-engine initialization. */
|
|
if (flags & HAS_ENGINE_MOCS)
|
|
init_mocs_table(engine, &table);
|
|
|
|
if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
|
|
init_l3cc_table(engine, &table);
|
|
}
|
|
|
|
static u32 global_mocs_offset(void)
|
|
{
|
|
return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
|
|
}
|
|
|
|
void intel_mocs_init(struct intel_gt *gt)
|
|
{
|
|
struct drm_i915_mocs_table table;
|
|
unsigned int flags;
|
|
|
|
/*
|
|
* LLC and eDRAM control values are not applicable to dgfx
|
|
*/
|
|
flags = get_mocs_settings(gt->i915, &table);
|
|
if (flags & HAS_GLOBAL_MOCS)
|
|
__init_mocs_table(gt->uncore, &table, global_mocs_offset());
|
|
}
|
|
|
|
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
|
|
#include "selftest_mocs.c"
|
|
#endif
|