164 lines
4.0 KiB
C
164 lines
4.0 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#include <linux/cpufreq.h>
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#include "i915_drv.h"
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#include "intel_gt.h"
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#include "intel_llc.h"
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#include "intel_sideband.h"
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struct ia_constants {
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unsigned int min_gpu_freq;
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unsigned int max_gpu_freq;
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unsigned int min_ring_freq;
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unsigned int max_ia_freq;
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};
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static struct intel_gt *llc_to_gt(struct intel_llc *llc)
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{
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return container_of(llc, struct intel_gt, llc);
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}
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static unsigned int cpu_max_MHz(void)
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{
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struct cpufreq_policy *policy;
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unsigned int max_khz;
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policy = cpufreq_cpu_get(0);
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if (policy) {
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max_khz = policy->cpuinfo.max_freq;
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cpufreq_cpu_put(policy);
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} else {
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/*
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* Default to measured freq if none found, PCU will ensure we
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* don't go over
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*/
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max_khz = tsc_khz;
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}
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return max_khz / 1000;
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}
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static bool get_ia_constants(struct intel_llc *llc,
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struct ia_constants *consts)
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{
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struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
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struct intel_rps *rps = &llc_to_gt(llc)->rps;
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if (!HAS_LLC(i915) || IS_DGFX(i915))
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return false;
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if (rps->max_freq <= rps->min_freq)
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return false;
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consts->max_ia_freq = cpu_max_MHz();
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consts->min_ring_freq =
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intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf;
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/* convert DDR frequency from units of 266.6MHz to bandwidth */
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consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
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consts->min_gpu_freq = rps->min_freq;
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consts->max_gpu_freq = rps->max_freq;
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if (INTEL_GEN(i915) >= 9) {
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/* Convert GT frequency to 50 HZ units */
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consts->min_gpu_freq /= GEN9_FREQ_SCALER;
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consts->max_gpu_freq /= GEN9_FREQ_SCALER;
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}
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return true;
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}
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static void calc_ia_freq(struct intel_llc *llc,
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unsigned int gpu_freq,
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const struct ia_constants *consts,
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unsigned int *out_ia_freq,
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unsigned int *out_ring_freq)
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{
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struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
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const int diff = consts->max_gpu_freq - gpu_freq;
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unsigned int ia_freq = 0, ring_freq = 0;
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if (INTEL_GEN(i915) >= 9) {
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/*
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* ring_freq = 2 * GT. ring_freq is in 100MHz units
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* No floor required for ring frequency on SKL.
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*/
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ring_freq = gpu_freq;
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} else if (INTEL_GEN(i915) >= 8) {
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/* max(2 * GT, DDR). NB: GT is 50MHz units */
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ring_freq = max(consts->min_ring_freq, gpu_freq);
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} else if (IS_HASWELL(i915)) {
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ring_freq = mult_frac(gpu_freq, 5, 4);
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ring_freq = max(consts->min_ring_freq, ring_freq);
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/* leave ia_freq as the default, chosen by cpufreq */
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} else {
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const int min_freq = 15;
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const int scale = 180;
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/*
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* On older processors, there is no separate ring
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* clock domain, so in order to boost the bandwidth
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* of the ring, we need to upclock the CPU (ia_freq).
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*
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* For GPU frequencies less than 750MHz,
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* just use the lowest ring freq.
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*/
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if (gpu_freq < min_freq)
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ia_freq = 800;
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else
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ia_freq = consts->max_ia_freq - diff * scale / 2;
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ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
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}
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*out_ia_freq = ia_freq;
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*out_ring_freq = ring_freq;
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}
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static void gen6_update_ring_freq(struct intel_llc *llc)
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{
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struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
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struct ia_constants consts;
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unsigned int gpu_freq;
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if (!get_ia_constants(llc, &consts))
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return;
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/*
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* For each potential GPU frequency, load a ring frequency we'd like
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* to use for memory access. We do this by specifying the IA frequency
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* the PCU should use as a reference to determine the ring frequency.
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*/
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for (gpu_freq = consts.max_gpu_freq;
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gpu_freq >= consts.min_gpu_freq;
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gpu_freq--) {
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unsigned int ia_freq, ring_freq;
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calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
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sandybridge_pcode_write(i915,
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GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
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ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
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ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
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gpu_freq);
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}
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}
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void intel_llc_enable(struct intel_llc *llc)
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{
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gen6_update_ring_freq(llc);
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}
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void intel_llc_disable(struct intel_llc *llc)
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{
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/* Currently there is no HW configuration to be done to disable. */
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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#include "selftest_llc.c"
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#endif
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