804 lines
27 KiB
C
804 lines
27 KiB
C
/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright (c) 2007-2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef __INTEL_DRV_H__
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#define __INTEL_DRV_H__
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#include <linux/i2c.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_dp_helper.h>
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/**
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* _wait_for - magic (register) wait macro
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*
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* Does the right thing for modeset paths when run under kdgb or similar atomic
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* contexts. Note that it's important that we check the condition again after
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* having timed out, since the timeout could be due to preemption or similar and
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* we've never had a chance to check the condition before the timeout.
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*/
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#define _wait_for(COND, MS, W) ({ \
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unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
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int ret__ = 0; \
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while (!(COND)) { \
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if (time_after(jiffies, timeout__)) { \
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if (!(COND)) \
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ret__ = -ETIMEDOUT; \
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break; \
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} \
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if (W && drm_can_sleep()) { \
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msleep(W); \
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} else { \
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cpu_relax(); \
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} \
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} \
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ret__; \
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})
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#define wait_for(COND, MS) _wait_for(COND, MS, 1)
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#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
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#define wait_for_atomic_us(COND, US) _wait_for((COND), \
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DIV_ROUND_UP((US), 1000), 0)
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#define KHz(x) (1000*x)
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#define MHz(x) KHz(1000*x)
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/*
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* Display related stuff
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*/
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/* store information about an Ixxx DVO */
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/* The i830->i865 use multiple DVOs with multiple i2cs */
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/* the i915, i945 have a single sDVO i2c bus - which is different */
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#define MAX_OUTPUTS 6
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/* maximum connectors per crtcs in the mode set */
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#define INTELFB_CONN_LIMIT 4
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#define INTEL_I2C_BUS_DVO 1
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#define INTEL_I2C_BUS_SDVO 2
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/* these are outputs from the chip - integrated only
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external chips are via DVO or SDVO output */
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#define INTEL_OUTPUT_UNUSED 0
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#define INTEL_OUTPUT_ANALOG 1
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#define INTEL_OUTPUT_DVO 2
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#define INTEL_OUTPUT_SDVO 3
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#define INTEL_OUTPUT_LVDS 4
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#define INTEL_OUTPUT_TVOUT 5
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#define INTEL_OUTPUT_HDMI 6
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#define INTEL_OUTPUT_DISPLAYPORT 7
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#define INTEL_OUTPUT_EDP 8
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#define INTEL_OUTPUT_UNKNOWN 9
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#define INTEL_DVO_CHIP_NONE 0
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#define INTEL_DVO_CHIP_LVDS 1
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#define INTEL_DVO_CHIP_TMDS 2
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#define INTEL_DVO_CHIP_TVOUT 4
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struct intel_framebuffer {
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struct drm_framebuffer base;
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struct drm_i915_gem_object *obj;
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};
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struct intel_fbdev {
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struct drm_fb_helper helper;
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struct intel_framebuffer ifb;
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struct list_head fbdev_list;
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struct drm_display_mode *our_mode;
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};
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struct intel_encoder {
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struct drm_encoder base;
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/*
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* The new crtc this encoder will be driven from. Only differs from
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* base->crtc while a modeset is in progress.
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*/
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struct intel_crtc *new_crtc;
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int type;
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/*
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* Intel hw has only one MUX where encoders could be clone, hence a
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* simple flag is enough to compute the possible_clones mask.
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*/
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bool cloneable;
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bool connectors_active;
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void (*hot_plug)(struct intel_encoder *);
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bool (*compute_config)(struct intel_encoder *,
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struct intel_crtc_config *);
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void (*pre_pll_enable)(struct intel_encoder *);
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void (*pre_enable)(struct intel_encoder *);
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void (*enable)(struct intel_encoder *);
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void (*mode_set)(struct intel_encoder *intel_encoder);
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void (*disable)(struct intel_encoder *);
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void (*post_disable)(struct intel_encoder *);
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/* Read out the current hw state of this connector, returning true if
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* the encoder is active. If the encoder is enabled it also set the pipe
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* it is connected to in the pipe parameter. */
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bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
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/* Reconstructs the equivalent mode flags for the current hardware
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* state. */
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void (*get_config)(struct intel_encoder *,
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struct intel_crtc_config *pipe_config);
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int crtc_mask;
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enum hpd_pin hpd_pin;
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};
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struct intel_panel {
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struct drm_display_mode *fixed_mode;
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int fitting_mode;
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};
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struct intel_connector {
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struct drm_connector base;
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/*
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* The fixed encoder this connector is connected to.
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*/
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struct intel_encoder *encoder;
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/*
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* The new encoder this connector will be driven. Only differs from
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* encoder while a modeset is in progress.
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*/
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struct intel_encoder *new_encoder;
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/* Reads out the current hw, returning true if the connector is enabled
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* and active (i.e. dpms ON state). */
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bool (*get_hw_state)(struct intel_connector *);
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/* Panel info for eDP and LVDS */
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struct intel_panel panel;
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/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
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struct edid *edid;
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/* since POLL and HPD connectors may use the same HPD line keep the native
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state of connector->polled in case hotplug storm detection changes it */
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u8 polled;
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};
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typedef struct dpll {
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/* given values */
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int n;
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int m1, m2;
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int p1, p2;
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/* derived values */
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int dot;
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int vco;
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int m;
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int p;
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} intel_clock_t;
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struct intel_crtc_config {
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struct drm_display_mode requested_mode;
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struct drm_display_mode adjusted_mode;
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/* This flag must be set by the encoder's compute_config callback if it
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* changes the crtc timings in the mode to prevent the crtc fixup from
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* overwriting them. Currently only lvds needs that. */
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bool timings_set;
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/* Whether to set up the PCH/FDI. Note that we never allow sharing
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* between pch encoders and cpu encoders. */
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bool has_pch_encoder;
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/* CPU Transcoder for the pipe. Currently this can only differ from the
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* pipe on Haswell (where we have a special eDP transcoder). */
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enum transcoder cpu_transcoder;
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/*
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* Use reduced/limited/broadcast rbg range, compressing from the full
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* range fed into the crtcs.
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*/
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bool limited_color_range;
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/* DP has a bunch of special case unfortunately, so mark the pipe
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* accordingly. */
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bool has_dp_encoder;
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/*
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* Enable dithering, used when the selected pipe bpp doesn't match the
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* plane bpp.
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*/
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bool dither;
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/* Controls for the clock computation, to override various stages. */
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bool clock_set;
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/* SDVO TV has a bunch of special case. To make multifunction encoders
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* work correctly, we need to track this at runtime.*/
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bool sdvo_tv_clock;
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/*
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* crtc bandwidth limit, don't increase pipe bpp or clock if not really
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* required. This is set in the 2nd loop of calling encoder's
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* ->compute_config if the first pick doesn't work out.
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*/
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bool bw_constrained;
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/* Settings for the intel dpll used on pretty much everything but
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* haswell. */
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struct dpll dpll;
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int pipe_bpp;
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struct intel_link_m_n dp_m_n;
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/**
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* This is currently used by DP and HDMI encoders since those can have a
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* target pixel clock != the port link clock (which is currently stored
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* in adjusted_mode->clock).
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*/
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int pixel_target_clock;
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/* Used by SDVO (and if we ever fix it, HDMI). */
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unsigned pixel_multiplier;
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/* Panel fitter controls for gen2-gen4 + VLV */
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struct {
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u32 control;
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u32 pgm_ratios;
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u32 lvds_border_bits;
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} gmch_pfit;
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/* Panel fitter placement and size for Ironlake+ */
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struct {
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u32 pos;
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u32 size;
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} pch_pfit;
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/* FDI configuration, only valid if has_pch_encoder is set. */
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int fdi_lanes;
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struct intel_link_m_n fdi_m_n;
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};
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struct intel_crtc {
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struct drm_crtc base;
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enum pipe pipe;
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enum plane plane;
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u8 lut_r[256], lut_g[256], lut_b[256];
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/*
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* Whether the crtc and the connected output pipeline is active. Implies
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* that crtc->enabled is set, i.e. the current mode configuration has
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* some outputs connected to this crtc.
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*/
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bool active;
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bool eld_vld;
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bool primary_disabled; /* is the crtc obscured by a plane? */
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bool lowfreq_avail;
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struct intel_overlay *overlay;
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struct intel_unpin_work *unpin_work;
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atomic_t unpin_work_count;
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/* Display surface base address adjustement for pageflips. Note that on
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* gen4+ this only adjusts up to a tile, offsets within a tile are
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* handled in the hw itself (with the TILEOFF register). */
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unsigned long dspaddr_offset;
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struct drm_i915_gem_object *cursor_bo;
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uint32_t cursor_addr;
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int16_t cursor_x, cursor_y;
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int16_t cursor_width, cursor_height;
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bool cursor_visible;
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struct intel_crtc_config config;
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/* We can share PLLs across outputs if the timings match */
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struct intel_pch_pll *pch_pll;
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uint32_t ddi_pll_sel;
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/* reset counter value when the last flip was submitted */
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unsigned int reset_counter;
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/* Access to these should be protected by dev_priv->irq_lock. */
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bool cpu_fifo_underrun_disabled;
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bool pch_fifo_underrun_disabled;
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};
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struct intel_plane {
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struct drm_plane base;
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int plane;
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enum pipe pipe;
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struct drm_i915_gem_object *obj;
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bool can_scale;
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int max_downscale;
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u32 lut_r[1024], lut_g[1024], lut_b[1024];
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int crtc_x, crtc_y;
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unsigned int crtc_w, crtc_h;
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uint32_t src_x, src_y;
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uint32_t src_w, src_h;
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/* Since we need to change the watermarks before/after
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* enabling/disabling the planes, we need to store the parameters here
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* as the other pieces of the struct may not reflect the values we want
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* for the watermark calculations. Currently only Haswell uses this.
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*/
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struct {
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bool enable;
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uint8_t bytes_per_pixel;
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uint32_t horiz_pixels;
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} wm;
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void (*update_plane)(struct drm_plane *plane,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj,
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int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t x, uint32_t y,
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uint32_t src_w, uint32_t src_h);
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void (*disable_plane)(struct drm_plane *plane);
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int (*update_colorkey)(struct drm_plane *plane,
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struct drm_intel_sprite_colorkey *key);
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void (*get_colorkey)(struct drm_plane *plane,
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struct drm_intel_sprite_colorkey *key);
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};
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struct intel_watermark_params {
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unsigned long fifo_size;
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unsigned long max_wm;
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unsigned long default_wm;
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unsigned long guard_size;
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unsigned long cacheline_size;
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};
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struct cxsr_latency {
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int is_desktop;
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int is_ddr3;
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unsigned long fsb_freq;
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unsigned long mem_freq;
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unsigned long display_sr;
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unsigned long display_hpll_disable;
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unsigned long cursor_sr;
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unsigned long cursor_hpll_disable;
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};
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#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
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#define to_intel_connector(x) container_of(x, struct intel_connector, base)
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#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
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#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
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#define to_intel_plane(x) container_of(x, struct intel_plane, base)
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#define DIP_HEADER_SIZE 5
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#define DIP_TYPE_AVI 0x82
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#define DIP_VERSION_AVI 0x2
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#define DIP_LEN_AVI 13
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#define DIP_AVI_PR_1 0
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#define DIP_AVI_PR_2 1
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#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
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#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
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#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
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#define DIP_TYPE_SPD 0x83
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#define DIP_VERSION_SPD 0x1
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#define DIP_LEN_SPD 25
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#define DIP_SPD_UNKNOWN 0
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#define DIP_SPD_DSTB 0x1
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#define DIP_SPD_DVDP 0x2
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#define DIP_SPD_DVHS 0x3
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#define DIP_SPD_HDDVR 0x4
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#define DIP_SPD_DVC 0x5
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#define DIP_SPD_DSC 0x6
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#define DIP_SPD_VCD 0x7
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#define DIP_SPD_GAME 0x8
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#define DIP_SPD_PC 0x9
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#define DIP_SPD_BD 0xa
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#define DIP_SPD_SCD 0xb
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struct dip_infoframe {
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uint8_t type; /* HB0 */
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uint8_t ver; /* HB1 */
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uint8_t len; /* HB2 - body len, not including checksum */
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uint8_t ecc; /* Header ECC */
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uint8_t checksum; /* PB0 */
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union {
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struct {
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/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
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uint8_t Y_A_B_S;
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/* PB2 - C 7:6, M 5:4, R 3:0 */
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uint8_t C_M_R;
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/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
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uint8_t ITC_EC_Q_SC;
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/* PB4 - VIC 6:0 */
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uint8_t VIC;
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/* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
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uint8_t YQ_CN_PR;
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/* PB6 to PB13 */
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uint16_t top_bar_end;
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uint16_t bottom_bar_start;
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uint16_t left_bar_end;
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uint16_t right_bar_start;
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} __attribute__ ((packed)) avi;
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struct {
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uint8_t vn[8];
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uint8_t pd[16];
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uint8_t sdi;
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} __attribute__ ((packed)) spd;
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uint8_t payload[27];
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} __attribute__ ((packed)) body;
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} __attribute__((packed));
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struct intel_hdmi {
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u32 hdmi_reg;
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int ddc_bus;
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uint32_t color_range;
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bool color_range_auto;
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bool has_hdmi_sink;
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bool has_audio;
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enum hdmi_force_audio force_audio;
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bool rgb_quant_range_selectable;
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void (*write_infoframe)(struct drm_encoder *encoder,
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struct dip_infoframe *frame);
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void (*set_infoframes)(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode);
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};
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#define DP_MAX_DOWNSTREAM_PORTS 0x10
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#define DP_LINK_CONFIGURATION_SIZE 9
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struct intel_dp {
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uint32_t output_reg;
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uint32_t aux_ch_ctl_reg;
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uint32_t DP;
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uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
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bool has_audio;
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enum hdmi_force_audio force_audio;
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uint32_t color_range;
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bool color_range_auto;
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uint8_t link_bw;
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uint8_t lane_count;
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uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
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uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
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struct i2c_adapter adapter;
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struct i2c_algo_dp_aux_data algo;
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uint8_t train_set[4];
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int panel_power_up_delay;
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int panel_power_down_delay;
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int panel_power_cycle_delay;
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int backlight_on_delay;
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int backlight_off_delay;
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struct delayed_work panel_vdd_work;
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bool want_panel_vdd;
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struct intel_connector *attached_connector;
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};
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struct intel_digital_port {
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struct intel_encoder base;
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enum port port;
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u32 port_reversal;
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struct intel_dp dp;
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struct intel_hdmi hdmi;
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};
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static inline int
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vlv_dport_to_channel(struct intel_digital_port *dport)
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{
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switch (dport->port) {
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case PORT_B:
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return 0;
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case PORT_C:
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return 1;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline struct drm_crtc *
|
|
intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
return dev_priv->pipe_to_crtc_mapping[pipe];
|
|
}
|
|
|
|
static inline struct drm_crtc *
|
|
intel_get_crtc_for_plane(struct drm_device *dev, int plane)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
return dev_priv->plane_to_crtc_mapping[plane];
|
|
}
|
|
|
|
struct intel_unpin_work {
|
|
struct work_struct work;
|
|
struct drm_crtc *crtc;
|
|
struct drm_i915_gem_object *old_fb_obj;
|
|
struct drm_i915_gem_object *pending_flip_obj;
|
|
struct drm_pending_vblank_event *event;
|
|
atomic_t pending;
|
|
#define INTEL_FLIP_INACTIVE 0
|
|
#define INTEL_FLIP_PENDING 1
|
|
#define INTEL_FLIP_COMPLETE 2
|
|
bool enable_stall_check;
|
|
};
|
|
|
|
struct intel_fbc_work {
|
|
struct delayed_work work;
|
|
struct drm_crtc *crtc;
|
|
struct drm_framebuffer *fb;
|
|
int interval;
|
|
};
|
|
|
|
int intel_pch_rawclk(struct drm_device *dev);
|
|
|
|
int intel_connector_update_modes(struct drm_connector *connector,
|
|
struct edid *edid);
|
|
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
|
|
|
|
extern void intel_attach_force_audio_property(struct drm_connector *connector);
|
|
extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
|
|
|
|
extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
|
|
extern void intel_crt_init(struct drm_device *dev);
|
|
extern void intel_hdmi_init(struct drm_device *dev,
|
|
int hdmi_reg, enum port port);
|
|
extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
|
|
struct intel_connector *intel_connector);
|
|
extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
|
|
extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
|
|
struct intel_crtc_config *pipe_config);
|
|
extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
|
|
extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
|
|
bool is_sdvob);
|
|
extern void intel_dvo_init(struct drm_device *dev);
|
|
extern void intel_tv_init(struct drm_device *dev);
|
|
extern void intel_mark_busy(struct drm_device *dev);
|
|
extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
|
|
extern void intel_mark_idle(struct drm_device *dev);
|
|
extern bool intel_lvds_init(struct drm_device *dev);
|
|
extern bool intel_is_dual_link_lvds(struct drm_device *dev);
|
|
extern void intel_dp_init(struct drm_device *dev, int output_reg,
|
|
enum port port);
|
|
extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
|
|
struct intel_connector *intel_connector);
|
|
extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
|
|
extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
|
|
extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
|
|
extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
|
|
extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
|
|
extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
|
|
extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
|
|
extern bool intel_dp_compute_config(struct intel_encoder *encoder,
|
|
struct intel_crtc_config *pipe_config);
|
|
extern bool intel_dpd_is_edp(struct drm_device *dev);
|
|
extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
|
|
extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
|
|
extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
|
|
extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
|
|
extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
|
|
extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
|
|
extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
|
|
extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
|
|
enum plane plane);
|
|
|
|
/* intel_panel.c */
|
|
extern int intel_panel_init(struct intel_panel *panel,
|
|
struct drm_display_mode *fixed_mode);
|
|
extern void intel_panel_fini(struct intel_panel *panel);
|
|
|
|
extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
|
|
struct drm_display_mode *adjusted_mode);
|
|
extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
|
|
struct intel_crtc_config *pipe_config,
|
|
int fitting_mode);
|
|
extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
|
|
struct intel_crtc_config *pipe_config,
|
|
int fitting_mode);
|
|
extern void intel_panel_set_backlight(struct drm_device *dev,
|
|
u32 level, u32 max);
|
|
extern int intel_panel_setup_backlight(struct drm_connector *connector);
|
|
extern void intel_panel_enable_backlight(struct drm_device *dev,
|
|
enum pipe pipe);
|
|
extern void intel_panel_disable_backlight(struct drm_device *dev);
|
|
extern void intel_panel_destroy_backlight(struct drm_device *dev);
|
|
extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
|
|
|
|
struct intel_set_config {
|
|
struct drm_encoder **save_connector_encoders;
|
|
struct drm_crtc **save_encoder_crtcs;
|
|
|
|
bool fb_changed;
|
|
bool mode_changed;
|
|
};
|
|
|
|
extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
|
|
int x, int y, struct drm_framebuffer *old_fb);
|
|
extern void intel_modeset_disable(struct drm_device *dev);
|
|
extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
|
|
extern void intel_crtc_load_lut(struct drm_crtc *crtc);
|
|
extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
|
|
extern void intel_encoder_destroy(struct drm_encoder *encoder);
|
|
extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
|
|
extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
|
|
extern void intel_connector_dpms(struct drm_connector *, int mode);
|
|
extern bool intel_connector_get_hw_state(struct intel_connector *connector);
|
|
extern void intel_modeset_check_state(struct drm_device *dev);
|
|
extern void intel_plane_restore(struct drm_plane *plane);
|
|
|
|
|
|
static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
|
|
{
|
|
return to_intel_connector(connector)->encoder;
|
|
}
|
|
|
|
static inline struct intel_digital_port *
|
|
enc_to_dig_port(struct drm_encoder *encoder)
|
|
{
|
|
return container_of(encoder, struct intel_digital_port, base.base);
|
|
}
|
|
|
|
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
|
|
{
|
|
return &enc_to_dig_port(encoder)->dp;
|
|
}
|
|
|
|
static inline struct intel_digital_port *
|
|
dp_to_dig_port(struct intel_dp *intel_dp)
|
|
{
|
|
return container_of(intel_dp, struct intel_digital_port, dp);
|
|
}
|
|
|
|
static inline struct intel_digital_port *
|
|
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
|
|
{
|
|
return container_of(intel_hdmi, struct intel_digital_port, hdmi);
|
|
}
|
|
|
|
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
|
|
struct intel_digital_port *port);
|
|
|
|
extern void intel_connector_attach_encoder(struct intel_connector *connector,
|
|
struct intel_encoder *encoder);
|
|
extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
|
|
|
|
extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
|
|
struct drm_crtc *crtc);
|
|
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern enum transcoder
|
|
intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe);
|
|
extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
|
|
extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
|
|
extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
|
|
extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
|
|
|
|
struct intel_load_detect_pipe {
|
|
struct drm_framebuffer *release_fb;
|
|
bool load_detect_temp;
|
|
int dpms_mode;
|
|
};
|
|
extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
|
|
struct drm_display_mode *mode,
|
|
struct intel_load_detect_pipe *old);
|
|
extern void intel_release_load_detect_pipe(struct drm_connector *connector,
|
|
struct intel_load_detect_pipe *old);
|
|
|
|
extern void intelfb_restore(void);
|
|
extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
|
|
u16 blue, int regno);
|
|
extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
|
|
u16 *blue, int regno);
|
|
extern void intel_enable_clock_gating(struct drm_device *dev);
|
|
|
|
extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
|
|
struct drm_i915_gem_object *obj,
|
|
struct intel_ring_buffer *pipelined);
|
|
extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
|
|
|
|
extern int intel_framebuffer_init(struct drm_device *dev,
|
|
struct intel_framebuffer *ifb,
|
|
struct drm_mode_fb_cmd2 *mode_cmd,
|
|
struct drm_i915_gem_object *obj);
|
|
extern int intel_fbdev_init(struct drm_device *dev);
|
|
extern void intel_fbdev_initial_config(struct drm_device *dev);
|
|
extern void intel_fbdev_fini(struct drm_device *dev);
|
|
extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
|
|
extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
|
|
extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
|
|
extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
|
|
|
|
extern void intel_setup_overlay(struct drm_device *dev);
|
|
extern void intel_cleanup_overlay(struct drm_device *dev);
|
|
extern int intel_overlay_switch_off(struct intel_overlay *overlay);
|
|
extern int intel_overlay_put_image(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern int intel_overlay_attrs(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
|
|
extern void intel_fb_output_poll_changed(struct drm_device *dev);
|
|
extern void intel_fb_restore_mode(struct drm_device *dev);
|
|
|
|
extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
|
|
bool state);
|
|
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
|
|
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
|
|
|
|
extern void intel_init_clock_gating(struct drm_device *dev);
|
|
extern void intel_suspend_hw(struct drm_device *dev);
|
|
extern void intel_write_eld(struct drm_encoder *encoder,
|
|
struct drm_display_mode *mode);
|
|
extern void intel_prepare_ddi(struct drm_device *dev);
|
|
extern void hsw_fdi_link_train(struct drm_crtc *crtc);
|
|
extern void intel_ddi_init(struct drm_device *dev, enum port port);
|
|
|
|
/* For use by IVB LP watermark workaround in intel_sprite.c */
|
|
extern void intel_update_watermarks(struct drm_device *dev);
|
|
extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
|
|
uint32_t sprite_width,
|
|
int pixel_size, bool enable);
|
|
|
|
extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
|
|
unsigned int tiling_mode,
|
|
unsigned int bpp,
|
|
unsigned int pitch);
|
|
|
|
extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
|
|
/* Power-related functions, located in intel_pm.c */
|
|
extern void intel_init_pm(struct drm_device *dev);
|
|
/* FBC */
|
|
extern bool intel_fbc_enabled(struct drm_device *dev);
|
|
extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
|
|
extern void intel_update_fbc(struct drm_device *dev);
|
|
/* IPS */
|
|
extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
|
|
extern void intel_gpu_ips_teardown(void);
|
|
|
|
extern bool intel_display_power_enabled(struct drm_device *dev,
|
|
enum intel_display_power_domain domain);
|
|
extern void intel_init_power_well(struct drm_device *dev);
|
|
extern void intel_set_power_well(struct drm_device *dev, bool enable);
|
|
extern void intel_enable_gt_powersave(struct drm_device *dev);
|
|
extern void intel_disable_gt_powersave(struct drm_device *dev);
|
|
extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
|
|
extern void ironlake_teardown_rc6(struct drm_device *dev);
|
|
|
|
extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
|
|
enum pipe *pipe);
|
|
extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
|
|
extern void intel_ddi_pll_init(struct drm_device *dev);
|
|
extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
|
|
extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
|
|
enum transcoder cpu_transcoder);
|
|
extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
|
|
extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
|
|
extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
|
|
extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
|
|
extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
|
|
extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
|
|
extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
|
|
extern bool
|
|
intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
|
|
extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
|
|
|
|
extern void intel_display_handle_reset(struct drm_device *dev);
|
|
extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
|
|
enum pipe pipe,
|
|
bool enable);
|
|
extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
|
|
enum transcoder pch_transcoder,
|
|
bool enable);
|
|
|
|
#endif /* __INTEL_DRV_H__ */
|