256 lines
6.5 KiB
C
256 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Amlogic AXG MIPI + PCIE analog PHY driver
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*
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* Copyright (C) 2019 Remi Pommarel <repk@triplefau.lt>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/phy/phy.h>
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#define HHI_MIPI_CNTL0 0x00
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#define HHI_MIPI_CNTL0_COMMON_BLOCK GENMASK(31, 28)
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#define HHI_MIPI_CNTL0_ENABLE BIT(29)
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#define HHI_MIPI_CNTL0_BANDGAP BIT(26)
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#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(25, 16)
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#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
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#define HHI_MIPI_CNTL1 0x04
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#define HHI_MIPI_CNTL1_CH0_CML_PDR_EN BIT(12)
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#define HHI_MIPI_CNTL1_LP_ABILITY GENMASK(5, 4)
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#define HHI_MIPI_CNTL1_LP_RESISTER BIT(3)
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#define HHI_MIPI_CNTL1_INPUT_SETTING BIT(2)
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#define HHI_MIPI_CNTL1_INPUT_SEL BIT(1)
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#define HHI_MIPI_CNTL1_PRBS7_EN BIT(0)
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#define HHI_MIPI_CNTL2 0x08
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#define HHI_MIPI_CNTL2_CH_PU GENMASK(31, 25)
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#define HHI_MIPI_CNTL2_CH_CTL GENMASK(24, 19)
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#define HHI_MIPI_CNTL2_CH0_DIGDR_EN BIT(18)
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#define HHI_MIPI_CNTL2_CH_DIGDR_EN BIT(17)
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#define HHI_MIPI_CNTL2_LPULPS_EN BIT(16)
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#define HHI_MIPI_CNTL2_CH_EN GENMASK(15, 11)
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#define HHI_MIPI_CNTL2_CH0_LP_CTL GENMASK(10, 1)
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#define DSI_LANE_0 BIT(4)
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#define DSI_LANE_1 BIT(3)
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#define DSI_LANE_CLK BIT(2)
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#define DSI_LANE_2 BIT(1)
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#define DSI_LANE_3 BIT(0)
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struct phy_axg_mipi_pcie_analog_priv {
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struct phy *phy;
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struct regmap *regmap;
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bool dsi_configured;
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bool dsi_enabled;
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bool powered;
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struct phy_configure_opts_mipi_dphy config;
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};
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static void phy_bandgap_enable(struct phy_axg_mipi_pcie_analog_priv *priv)
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{
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_BANDGAP, HHI_MIPI_CNTL0_BANDGAP);
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_ENABLE, HHI_MIPI_CNTL0_ENABLE);
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}
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static void phy_bandgap_disable(struct phy_axg_mipi_pcie_analog_priv *priv)
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{
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_BANDGAP, 0);
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_ENABLE, 0);
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}
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static void phy_dsi_analog_enable(struct phy_axg_mipi_pcie_analog_priv *priv)
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{
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u32 reg;
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_DIF_REF_CTL1,
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FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0x1b8));
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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BIT(31), BIT(31));
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_DIF_REF_CTL0,
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FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8));
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regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0x001e);
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regmap_write(priv->regmap, HHI_MIPI_CNTL2,
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(0x26e0 << 16) | (0x459 << 0));
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reg = DSI_LANE_CLK;
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switch (priv->config.lanes) {
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case 4:
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reg |= DSI_LANE_3;
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fallthrough;
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case 3:
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reg |= DSI_LANE_2;
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fallthrough;
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case 2:
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reg |= DSI_LANE_1;
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fallthrough;
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case 1:
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reg |= DSI_LANE_0;
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break;
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default:
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reg = 0;
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}
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2,
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HHI_MIPI_CNTL2_CH_EN,
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FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg));
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priv->dsi_enabled = true;
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}
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static void phy_dsi_analog_disable(struct phy_axg_mipi_pcie_analog_priv *priv)
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{
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_DIF_REF_CTL1,
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FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0));
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0, BIT(31), 0);
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regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
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HHI_MIPI_CNTL0_DIF_REF_CTL1, 0);
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regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0x6);
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regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0x00200000);
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priv->dsi_enabled = false;
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}
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static int phy_axg_mipi_pcie_analog_configure(struct phy *phy,
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union phy_configure_opts *opts)
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{
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struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy);
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int ret;
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ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
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if (ret)
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return ret;
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memcpy(&priv->config, opts, sizeof(priv->config));
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priv->dsi_configured = true;
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/* If PHY was already powered on, setup the DSI analog part */
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if (priv->powered) {
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/* If reconfiguring, disable & reconfigure */
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if (priv->dsi_enabled)
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phy_dsi_analog_disable(priv);
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usleep_range(100, 200);
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phy_dsi_analog_enable(priv);
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}
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return 0;
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}
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static int phy_axg_mipi_pcie_analog_power_on(struct phy *phy)
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{
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struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy);
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phy_bandgap_enable(priv);
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if (priv->dsi_configured)
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phy_dsi_analog_enable(priv);
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priv->powered = true;
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return 0;
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}
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static int phy_axg_mipi_pcie_analog_power_off(struct phy *phy)
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{
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struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy);
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phy_bandgap_disable(priv);
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if (priv->dsi_enabled)
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phy_dsi_analog_disable(priv);
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priv->powered = false;
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return 0;
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}
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static const struct phy_ops phy_axg_mipi_pcie_analog_ops = {
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.configure = phy_axg_mipi_pcie_analog_configure,
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.power_on = phy_axg_mipi_pcie_analog_power_on,
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.power_off = phy_axg_mipi_pcie_analog_power_off,
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.owner = THIS_MODULE,
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};
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static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy;
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struct device *dev = &pdev->dev;
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struct phy_axg_mipi_pcie_analog_priv *priv;
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struct device_node *np = dev->of_node, *parent_np;
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struct regmap *map;
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int ret;
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priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* Get the hhi system controller node */
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parent_np = of_get_parent(dev->of_node);
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map = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(map)) {
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dev_err(dev,
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"failed to get HHI regmap\n");
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return PTR_ERR(map);
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}
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priv->regmap = map;
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priv->phy = devm_phy_create(dev, np, &phy_axg_mipi_pcie_analog_ops);
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if (IS_ERR(priv->phy)) {
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ret = PTR_ERR(priv->phy);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "failed to create PHY\n");
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return ret;
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}
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phy_set_drvdata(priv->phy, priv);
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dev_set_drvdata(dev, priv);
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phy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy);
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}
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static const struct of_device_id phy_axg_mipi_pcie_analog_of_match[] = {
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{
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.compatible = "amlogic,axg-mipi-pcie-analog-phy",
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, phy_axg_mipi_pcie_analog_of_match);
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static struct platform_driver phy_axg_mipi_pcie_analog_driver = {
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.probe = phy_axg_mipi_pcie_analog_probe,
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.driver = {
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.name = "phy-axg-mipi-pcie-analog",
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.of_match_table = phy_axg_mipi_pcie_analog_of_match,
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},
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};
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module_platform_driver(phy_axg_mipi_pcie_analog_driver);
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MODULE_AUTHOR("Remi Pommarel <repk@triplefau.lt>");
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MODULE_DESCRIPTION("Amlogic AXG MIPI + PCIE analog PHY driver");
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MODULE_LICENSE("GPL v2");
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