429 lines
11 KiB
C
429 lines
11 KiB
C
/****************************************************************************
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Copyright Echo Digital Audio Corporation (c) 1998 - 2004
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All rights reserved
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www.echoaudio.com
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This file is part of Echo Digital Audio's generic driver library.
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Echo Digital Audio's generic driver library is free software;
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you can redistribute it and/or modify it under the terms of
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the GNU General Public License as published by the Free Software
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Foundation.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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MA 02111-1307, USA.
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*************************************************************************
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Translation from C++ and adaptation for use in ALSA-Driver
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were made by Giuliano Pochini <pochini@shiny.it>
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****************************************************************************/
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static int write_control_reg(struct echoaudio *chip, u32 value, char force);
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static int set_input_clock(struct echoaudio *chip, u16 clock);
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static int set_professional_spdif(struct echoaudio *chip, char prof);
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static int set_digital_mode(struct echoaudio *chip, u8 mode);
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static int load_asic_generic(struct echoaudio *chip, u32 cmd,
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const struct firmware *asic);
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static int check_asic_status(struct echoaudio *chip);
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static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
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{
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int err;
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DE_INIT(("init_hw() - Mona\n"));
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snd_assert((subdevice_id & 0xfff0) == MONA, return -ENODEV);
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if ((err = init_dsp_comm_page(chip))) {
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DE_INIT(("init_hw - could not initialize DSP comm page\n"));
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return err;
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}
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chip->device_id = device_id;
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chip->subdevice_id = subdevice_id;
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chip->bad_board = TRUE;
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chip->input_clock_types =
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ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
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ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT;
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chip->digital_modes =
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ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
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ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
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ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
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/* Mona comes in both '301 and '361 flavors */
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if (chip->device_id == DEVICE_ID_56361)
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chip->dsp_code_to_load = &card_fw[FW_MONA_361_DSP];
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else
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chip->dsp_code_to_load = &card_fw[FW_MONA_301_DSP];
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chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
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chip->professional_spdif = FALSE;
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chip->digital_in_automute = TRUE;
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if ((err = load_firmware(chip)) < 0)
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return err;
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chip->bad_board = FALSE;
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if ((err = init_line_levels(chip)) < 0)
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return err;
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err = set_digital_mode(chip, DIGITAL_MODE_SPDIF_RCA);
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snd_assert(err >= 0, return err);
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err = set_professional_spdif(chip, TRUE);
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DE_INIT(("init_hw done\n"));
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return err;
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}
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static u32 detect_input_clocks(const struct echoaudio *chip)
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{
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u32 clocks_from_dsp, clock_bits;
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/* Map the DSP clock detect bits to the generic driver clock
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detect bits */
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clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
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clock_bits = ECHO_CLOCK_BIT_INTERNAL;
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if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
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clock_bits |= ECHO_CLOCK_BIT_SPDIF;
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if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
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clock_bits |= ECHO_CLOCK_BIT_ADAT;
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if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD)
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clock_bits |= ECHO_CLOCK_BIT_WORD;
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return clock_bits;
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}
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/* Mona has an ASIC on the PCI card and another ASIC in the external box;
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both need to be loaded. */
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static int load_asic(struct echoaudio *chip)
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{
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u32 control_reg;
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int err;
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const struct firmware *asic;
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if (chip->asic_loaded)
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return 0;
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mdelay(10);
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if (chip->device_id == DEVICE_ID_56361)
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asic = &card_fw[FW_MONA_361_1_ASIC48];
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else
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asic = &card_fw[FW_MONA_301_1_ASIC48];
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err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic);
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if (err < 0)
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return err;
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chip->asic_code = asic;
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mdelay(10);
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/* Do the external one */
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err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_EXTERNAL_ASIC,
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&card_fw[FW_MONA_2_ASIC]);
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if (err < 0)
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return err;
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mdelay(10);
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err = check_asic_status(chip);
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/* Set up the control register if the load succeeded -
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48 kHz, internal clock, S/PDIF RCA mode */
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if (!err) {
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control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
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err = write_control_reg(chip, control_reg, TRUE);
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}
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return err;
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}
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/* Depending on what digital mode you want, Mona needs different ASICs
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loaded. This function checks the ASIC needed for the new mode and sees
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if it matches the one already loaded. */
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static int switch_asic(struct echoaudio *chip, char double_speed)
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{
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const struct firmware *asic;
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int err;
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/* Check the clock detect bits to see if this is
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a single-speed clock or a double-speed clock; load
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a new ASIC if necessary. */
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if (chip->device_id == DEVICE_ID_56361) {
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if (double_speed)
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asic = &card_fw[FW_MONA_361_1_ASIC96];
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else
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asic = &card_fw[FW_MONA_361_1_ASIC48];
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} else {
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if (double_speed)
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asic = &card_fw[FW_MONA_301_1_ASIC96];
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else
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asic = &card_fw[FW_MONA_301_1_ASIC48];
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}
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if (asic != chip->asic_code) {
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/* Load the desired ASIC */
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err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
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asic);
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if (err < 0)
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return err;
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chip->asic_code = asic;
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}
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return 0;
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}
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static int set_sample_rate(struct echoaudio *chip, u32 rate)
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{
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u32 control_reg, clock;
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const struct firmware *asic;
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char force_write;
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/* Only set the clock for internal mode. */
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if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
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DE_ACT(("set_sample_rate: Cannot set sample rate - "
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"clock not set to CLK_CLOCKININTERNAL\n"));
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/* Save the rate anyhow */
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chip->comm_page->sample_rate = cpu_to_le32(rate);
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chip->sample_rate = rate;
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return 0;
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}
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/* Now, check to see if the required ASIC is loaded */
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if (rate >= 88200) {
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if (chip->digital_mode == DIGITAL_MODE_ADAT)
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return -EINVAL;
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if (chip->device_id == DEVICE_ID_56361)
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asic = &card_fw[FW_MONA_361_1_ASIC96];
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else
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asic = &card_fw[FW_MONA_301_1_ASIC96];
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} else {
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if (chip->device_id == DEVICE_ID_56361)
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asic = &card_fw[FW_MONA_361_1_ASIC48];
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else
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asic = &card_fw[FW_MONA_301_1_ASIC48];
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}
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force_write = 0;
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if (asic != chip->asic_code) {
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int err;
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/* Load the desired ASIC (load_asic_generic() can sleep) */
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spin_unlock_irq(&chip->lock);
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err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
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asic);
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spin_lock_irq(&chip->lock);
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if (err < 0)
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return err;
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chip->asic_code = asic;
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force_write = 1;
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}
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/* Compute the new control register value */
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clock = 0;
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control_reg = le32_to_cpu(chip->comm_page->control_register);
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control_reg &= GML_CLOCK_CLEAR_MASK;
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control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
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switch (rate) {
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case 96000:
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clock = GML_96KHZ;
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break;
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case 88200:
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clock = GML_88KHZ;
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break;
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case 48000:
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clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
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break;
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case 44100:
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clock = GML_44KHZ;
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/* Professional mode */
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if (control_reg & GML_SPDIF_PRO_MODE)
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clock |= GML_SPDIF_SAMPLE_RATE0;
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break;
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case 32000:
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clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
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GML_SPDIF_SAMPLE_RATE1;
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break;
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case 22050:
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clock = GML_22KHZ;
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break;
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case 16000:
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clock = GML_16KHZ;
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break;
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case 11025:
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clock = GML_11KHZ;
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break;
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case 8000:
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clock = GML_8KHZ;
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break;
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default:
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DE_ACT(("set_sample_rate: %d invalid!\n", rate));
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return -EINVAL;
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}
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control_reg |= clock;
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chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */
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chip->sample_rate = rate;
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DE_ACT(("set_sample_rate: %d clock %d\n", rate, clock));
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return write_control_reg(chip, control_reg, force_write);
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}
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static int set_input_clock(struct echoaudio *chip, u16 clock)
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{
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u32 control_reg, clocks_from_dsp;
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int err;
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DE_ACT(("set_input_clock:\n"));
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/* Prevent two simultaneous calls to switch_asic() */
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if (atomic_read(&chip->opencount))
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return -EAGAIN;
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/* Mask off the clock select bits */
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control_reg = le32_to_cpu(chip->comm_page->control_register) &
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GML_CLOCK_CLEAR_MASK;
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clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
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switch (clock) {
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case ECHO_CLOCK_INTERNAL:
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DE_ACT(("Set Mona clock to INTERNAL\n"));
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chip->input_clock = ECHO_CLOCK_INTERNAL;
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return set_sample_rate(chip, chip->sample_rate);
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case ECHO_CLOCK_SPDIF:
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if (chip->digital_mode == DIGITAL_MODE_ADAT)
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return -EAGAIN;
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spin_unlock_irq(&chip->lock);
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err = switch_asic(chip, clocks_from_dsp &
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GML_CLOCK_DETECT_BIT_SPDIF96);
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spin_lock_irq(&chip->lock);
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if (err < 0)
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return err;
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DE_ACT(("Set Mona clock to SPDIF\n"));
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control_reg |= GML_SPDIF_CLOCK;
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if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96)
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control_reg |= GML_DOUBLE_SPEED_MODE;
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else
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control_reg &= ~GML_DOUBLE_SPEED_MODE;
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break;
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case ECHO_CLOCK_WORD:
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DE_ACT(("Set Mona clock to WORD\n"));
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spin_unlock_irq(&chip->lock);
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err = switch_asic(chip, clocks_from_dsp &
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GML_CLOCK_DETECT_BIT_WORD96);
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spin_lock_irq(&chip->lock);
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if (err < 0)
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return err;
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control_reg |= GML_WORD_CLOCK;
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if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96)
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control_reg |= GML_DOUBLE_SPEED_MODE;
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else
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control_reg &= ~GML_DOUBLE_SPEED_MODE;
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break;
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case ECHO_CLOCK_ADAT:
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DE_ACT(("Set Mona clock to ADAT\n"));
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if (chip->digital_mode != DIGITAL_MODE_ADAT)
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return -EAGAIN;
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control_reg |= GML_ADAT_CLOCK;
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control_reg &= ~GML_DOUBLE_SPEED_MODE;
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break;
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default:
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DE_ACT(("Input clock 0x%x not supported for Mona\n", clock));
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return -EINVAL;
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}
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chip->input_clock = clock;
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return write_control_reg(chip, control_reg, TRUE);
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}
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static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
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{
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u32 control_reg;
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int err, incompatible_clock;
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/* Set clock to "internal" if it's not compatible with the new mode */
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incompatible_clock = FALSE;
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switch (mode) {
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case DIGITAL_MODE_SPDIF_OPTICAL:
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case DIGITAL_MODE_SPDIF_RCA:
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if (chip->input_clock == ECHO_CLOCK_ADAT)
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incompatible_clock = TRUE;
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break;
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case DIGITAL_MODE_ADAT:
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if (chip->input_clock == ECHO_CLOCK_SPDIF)
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incompatible_clock = TRUE;
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break;
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default:
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DE_ACT(("Digital mode not supported: %d\n", mode));
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return -EINVAL;
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}
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spin_lock_irq(&chip->lock);
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if (incompatible_clock) { /* Switch to 48KHz, internal */
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chip->sample_rate = 48000;
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set_input_clock(chip, ECHO_CLOCK_INTERNAL);
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}
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/* Clear the current digital mode */
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control_reg = le32_to_cpu(chip->comm_page->control_register);
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control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
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/* Tweak the control reg */
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switch (mode) {
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case DIGITAL_MODE_SPDIF_OPTICAL:
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control_reg |= GML_SPDIF_OPTICAL_MODE;
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break;
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case DIGITAL_MODE_SPDIF_RCA:
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/* GML_SPDIF_OPTICAL_MODE bit cleared */
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break;
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case DIGITAL_MODE_ADAT:
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/* If the current ASIC is the 96KHz ASIC, switch the ASIC
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and set to 48 KHz */
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if (chip->asic_code == &card_fw[FW_MONA_361_1_ASIC96] ||
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chip->asic_code == &card_fw[FW_MONA_301_1_ASIC96]) {
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set_sample_rate(chip, 48000);
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}
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control_reg |= GML_ADAT_MODE;
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control_reg &= ~GML_DOUBLE_SPEED_MODE;
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break;
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}
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err = write_control_reg(chip, control_reg, FALSE);
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spin_unlock_irq(&chip->lock);
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if (err < 0)
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return err;
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chip->digital_mode = mode;
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DE_ACT(("set_digital_mode to %d\n", mode));
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return incompatible_clock;
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}
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