588 lines
19 KiB
C
588 lines
19 KiB
C
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2011 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _IXGBE_H_
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#define _IXGBE_H_
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#include <linux/bitops.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/cpumask.h>
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#include <linux/aer.h>
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#include <linux/if_vlan.h>
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#include "ixgbe_type.h"
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#include "ixgbe_common.h"
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#include "ixgbe_dcb.h"
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#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
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#define IXGBE_FCOE
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#include "ixgbe_fcoe.h"
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#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
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#ifdef CONFIG_IXGBE_DCA
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#include <linux/dca.h>
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#endif
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/* common prefix used by pr_<> macros */
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#undef pr_fmt
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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/* TX/RX descriptor defines */
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#define IXGBE_DEFAULT_TXD 512
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#define IXGBE_MAX_TXD 4096
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#define IXGBE_MIN_TXD 64
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#define IXGBE_DEFAULT_RXD 512
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#define IXGBE_MAX_RXD 4096
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#define IXGBE_MIN_RXD 64
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/* flow control */
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#define IXGBE_MIN_FCRTL 0x40
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#define IXGBE_MAX_FCRTL 0x7FF80
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#define IXGBE_MIN_FCRTH 0x600
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#define IXGBE_MAX_FCRTH 0x7FFF0
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#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
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#define IXGBE_MIN_FCPAUSE 0
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#define IXGBE_MAX_FCPAUSE 0xFFFF
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/* Supported Rx Buffer Sizes */
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#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
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#define IXGBE_RXBUFFER_2048 2048
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#define IXGBE_RXBUFFER_4096 4096
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#define IXGBE_RXBUFFER_8192 8192
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#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
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/*
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* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
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* reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
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* this adds up to 512 bytes of extra data meaning the smallest allocation
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* we could have is 1K.
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* i.e. RXBUFFER_512 --> size-1024 slab
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*/
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#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
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#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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#define IXGBE_TX_FLAGS_CSUM (u32)(1)
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#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
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#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
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#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
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#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
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#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
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#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
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#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
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#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
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#define IXGBE_MAX_RSC_INT_RATE 162760
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#define IXGBE_MAX_VF_MC_ENTRIES 30
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#define IXGBE_MAX_VF_FUNCTIONS 64
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#define IXGBE_MAX_VFTA_ENTRIES 128
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#define MAX_EMULATION_MAC_ADDRS 16
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#define IXGBE_MAX_PF_MACVLANS 15
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#define VMDQ_P(p) ((p) + adapter->num_vfs)
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struct vf_data_storage {
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unsigned char vf_mac_addresses[ETH_ALEN];
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u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
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u16 num_vf_mc_hashes;
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u16 default_vf_vlan_id;
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u16 vlans_enabled;
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bool clear_to_send;
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bool pf_set_mac;
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u16 pf_vlan; /* When set, guest VLAN config not allowed. */
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u16 pf_qos;
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u16 tx_rate;
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};
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struct vf_macvlans {
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struct list_head l;
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int vf;
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int rar_entry;
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bool free;
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bool is_macvlan;
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u8 vf_macvlan[ETH_ALEN];
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};
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/* wrapper around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer */
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struct ixgbe_tx_buffer {
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struct sk_buff *skb;
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dma_addr_t dma;
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unsigned long time_stamp;
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u16 length;
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u16 next_to_watch;
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unsigned int bytecount;
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u16 gso_segs;
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u8 mapped_as_page;
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};
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struct ixgbe_rx_buffer {
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struct sk_buff *skb;
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dma_addr_t dma;
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struct page *page;
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dma_addr_t page_dma;
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unsigned int page_offset;
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};
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struct ixgbe_queue_stats {
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u64 packets;
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u64 bytes;
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};
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struct ixgbe_tx_queue_stats {
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u64 restart_queue;
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u64 tx_busy;
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u64 completed;
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u64 tx_done_old;
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};
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struct ixgbe_rx_queue_stats {
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u64 rsc_count;
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u64 rsc_flush;
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u64 non_eop_descs;
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u64 alloc_rx_page_failed;
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u64 alloc_rx_buff_failed;
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};
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enum ixbge_ring_state_t {
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__IXGBE_TX_FDIR_INIT_DONE,
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__IXGBE_TX_DETECT_HANG,
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__IXGBE_HANG_CHECK_ARMED,
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__IXGBE_RX_PS_ENABLED,
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__IXGBE_RX_RSC_ENABLED,
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};
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#define ring_is_ps_enabled(ring) \
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test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
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#define set_ring_ps_enabled(ring) \
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set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
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#define clear_ring_ps_enabled(ring) \
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clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
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#define check_for_tx_hang(ring) \
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test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
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#define set_check_for_tx_hang(ring) \
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set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
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#define clear_check_for_tx_hang(ring) \
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clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
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#define ring_is_rsc_enabled(ring) \
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test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
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#define set_ring_rsc_enabled(ring) \
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set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
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#define clear_ring_rsc_enabled(ring) \
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clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
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struct ixgbe_ring {
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void *desc; /* descriptor ring memory */
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struct device *dev; /* device for DMA mapping */
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struct net_device *netdev; /* netdev ring belongs to */
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union {
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struct ixgbe_tx_buffer *tx_buffer_info;
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struct ixgbe_rx_buffer *rx_buffer_info;
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};
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unsigned long state;
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u8 atr_sample_rate;
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u8 atr_count;
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u16 count; /* amount of descriptors */
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u16 rx_buf_len;
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u16 next_to_use;
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u16 next_to_clean;
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u8 queue_index; /* needed for multiqueue queue management */
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u8 reg_idx; /* holds the special value that gets
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* the hardware register offset
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* associated with this ring, which is
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* different for DCB and RSS modes
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*/
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u8 dcb_tc;
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u16 work_limit; /* max work per interrupt */
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u8 __iomem *tail;
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unsigned int total_bytes;
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unsigned int total_packets;
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struct ixgbe_queue_stats stats;
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struct u64_stats_sync syncp;
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union {
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struct ixgbe_tx_queue_stats tx_stats;
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struct ixgbe_rx_queue_stats rx_stats;
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};
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int numa_node;
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unsigned int size; /* length in bytes */
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dma_addr_t dma; /* phys. address of descriptor ring */
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struct rcu_head rcu;
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struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
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} ____cacheline_internodealigned_in_smp;
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enum ixgbe_ring_f_enum {
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RING_F_NONE = 0,
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RING_F_DCB,
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RING_F_VMDQ, /* SR-IOV uses the same ring feature */
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RING_F_RSS,
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RING_F_FDIR,
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#ifdef IXGBE_FCOE
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RING_F_FCOE,
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#endif /* IXGBE_FCOE */
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RING_F_ARRAY_SIZE /* must be last in enum set */
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};
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#define IXGBE_MAX_DCB_INDICES 64
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#define IXGBE_MAX_RSS_INDICES 16
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#define IXGBE_MAX_VMDQ_INDICES 64
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#define IXGBE_MAX_FDIR_INDICES 64
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#ifdef IXGBE_FCOE
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#define IXGBE_MAX_FCOE_INDICES 8
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#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
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#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
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#else
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#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
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#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
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#endif /* IXGBE_FCOE */
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struct ixgbe_ring_feature {
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int indices;
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int mask;
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} ____cacheline_internodealigned_in_smp;
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#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
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? 8 : 1)
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#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
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/* MAX_MSIX_Q_VECTORS of these are allocated,
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* but we only use one per queue-specific vector.
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*/
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struct ixgbe_q_vector {
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struct ixgbe_adapter *adapter;
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unsigned int v_idx; /* index of q_vector within array, also used for
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* finding the bit in EICR and friends that
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* represents the vector for this ring */
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#ifdef CONFIG_IXGBE_DCA
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int cpu; /* CPU for DCA */
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#endif
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struct napi_struct napi;
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DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
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DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
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u8 rxr_count; /* Rx ring count assigned to this vector */
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u8 txr_count; /* Tx ring count assigned to this vector */
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u8 tx_itr;
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u8 rx_itr;
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u32 eitr;
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cpumask_var_t affinity_mask;
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char name[IFNAMSIZ + 9];
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};
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/* Helper macros to switch between ints/sec and what the register uses.
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* And yes, it's the same math going both ways. The lowest value
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* supported by all of the ixgbe hardware is 8.
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*/
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#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
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((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
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#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
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#define IXGBE_DESC_UNUSED(R) \
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((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
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(R)->next_to_clean - (R)->next_to_use - 1)
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#define IXGBE_RX_DESC_ADV(R, i) \
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(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
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#define IXGBE_TX_DESC_ADV(R, i) \
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(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
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#define IXGBE_TX_CTXTDESC_ADV(R, i) \
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(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
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#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
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#ifdef IXGBE_FCOE
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/* Use 3K as the baby jumbo frame size for FCoE */
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#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
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#endif /* IXGBE_FCOE */
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#define OTHER_VECTOR 1
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#define NON_Q_VECTORS (OTHER_VECTOR)
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#define MAX_MSIX_VECTORS_82599 64
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#define MAX_MSIX_Q_VECTORS_82599 64
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#define MAX_MSIX_VECTORS_82598 18
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#define MAX_MSIX_Q_VECTORS_82598 16
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#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
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#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
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#define MIN_MSIX_Q_VECTORS 2
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#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
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/* board specific private data structure */
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struct ixgbe_adapter {
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unsigned long state;
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/* Some features need tri-state capability,
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* thus the additional *_CAPABLE flags.
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*/
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u32 flags;
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#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
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#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
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#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
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#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
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#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
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#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
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#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
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#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
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#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
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#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
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#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
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#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
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#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
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#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
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#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
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#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
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#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
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#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
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#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
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#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
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#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
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#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
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#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
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#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
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#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
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#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
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#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
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u32 flags2;
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#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
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#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
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#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
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#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
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#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
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#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
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#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
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#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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u16 bd_number;
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struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
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/* DCB parameters */
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struct ieee_pfc *ixgbe_ieee_pfc;
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struct ieee_ets *ixgbe_ieee_ets;
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struct ixgbe_dcb_config dcb_cfg;
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struct ixgbe_dcb_config temp_dcb_cfg;
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u8 dcb_set_bitmap;
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u8 dcbx_cap;
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enum ixgbe_fc_mode last_lfc_mode;
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/* Interrupt Throttle Rate */
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u32 rx_itr_setting;
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u32 tx_itr_setting;
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u16 eitr_low;
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u16 eitr_high;
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/* TX */
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struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
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int num_tx_queues;
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u32 tx_timeout_count;
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bool detect_tx_hung;
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u64 restart_queue;
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u64 lsc_int;
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/* RX */
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struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
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int num_rx_queues;
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int num_rx_pools; /* == num_rx_queues in 82598 */
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int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
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u64 hw_csum_rx_error;
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u64 hw_rx_no_dma_resources;
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u64 non_eop_descs;
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int num_msix_vectors;
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int max_msix_q_vectors; /* true count of q_vectors for device */
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struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
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struct msix_entry *msix_entries;
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u32 alloc_rx_page_failed;
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u32 alloc_rx_buff_failed;
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/* default to trying for four seconds */
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#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
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/* OS defined structs */
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struct net_device *netdev;
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struct pci_dev *pdev;
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u32 test_icr;
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struct ixgbe_ring test_tx_ring;
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struct ixgbe_ring test_rx_ring;
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/* structs defined in ixgbe_hw.h */
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struct ixgbe_hw hw;
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u16 msg_enable;
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struct ixgbe_hw_stats stats;
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/* Interrupt Throttle Rate */
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u32 rx_eitr_param;
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u32 tx_eitr_param;
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u64 tx_busy;
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unsigned int tx_ring_count;
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unsigned int rx_ring_count;
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u32 link_speed;
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bool link_up;
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unsigned long link_check_timeout;
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struct work_struct service_task;
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struct timer_list service_timer;
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u32 fdir_pballoc;
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u32 atr_sample_rate;
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unsigned long fdir_overflow; /* number of times ATR was backed off */
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spinlock_t fdir_perfect_lock;
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#ifdef IXGBE_FCOE
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struct ixgbe_fcoe fcoe;
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#endif /* IXGBE_FCOE */
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u64 rsc_total_count;
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u64 rsc_total_flush;
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u32 wol;
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u16 eeprom_version;
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int node;
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u32 led_reg;
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u32 interrupt_event;
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char lsc_int_name[IFNAMSIZ + 9];
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/* SR-IOV */
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DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
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unsigned int num_vfs;
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struct vf_data_storage *vfinfo;
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int vf_rate_link_speed;
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struct vf_macvlans vf_mvs;
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struct vf_macvlans *mv_list;
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bool antispoofing_enabled;
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};
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enum ixbge_state_t {
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__IXGBE_TESTING,
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__IXGBE_RESETTING,
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__IXGBE_DOWN,
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__IXGBE_SERVICE_SCHED,
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__IXGBE_IN_SFP_INIT,
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};
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struct ixgbe_rsc_cb {
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dma_addr_t dma;
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u16 skb_cnt;
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bool delay_unmap;
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};
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#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
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enum ixgbe_boards {
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board_82598,
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board_82599,
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board_X540,
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};
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extern struct ixgbe_info ixgbe_82598_info;
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extern struct ixgbe_info ixgbe_82599_info;
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extern struct ixgbe_info ixgbe_X540_info;
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#ifdef CONFIG_IXGBE_DCB
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extern const struct dcbnl_rtnl_ops dcbnl_ops;
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extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
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struct ixgbe_dcb_config *dst_dcb_cfg,
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int tc_max);
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#endif
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extern char ixgbe_driver_name[];
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extern const char ixgbe_driver_version[];
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extern int ixgbe_up(struct ixgbe_adapter *adapter);
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extern void ixgbe_down(struct ixgbe_adapter *adapter);
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extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
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extern void ixgbe_reset(struct ixgbe_adapter *adapter);
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extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
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extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
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extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
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extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
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extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
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extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
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extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
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extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *);
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extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
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extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
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extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
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extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
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struct ixgbe_adapter *,
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struct ixgbe_ring *);
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extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
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struct ixgbe_tx_buffer *);
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extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
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extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
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extern int ethtool_ioctl(struct ifreq *ifr);
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extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
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extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
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extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_hash_dword input,
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union ixgbe_atr_hash_dword common,
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u8 queue);
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extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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struct ixgbe_atr_input_masks *input_masks,
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u16 soft_id, u8 queue);
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extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *ring);
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extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *ring);
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extern void ixgbe_set_rx_mode(struct net_device *netdev);
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extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
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#ifdef IXGBE_FCOE
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extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
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extern int ixgbe_fso(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *tx_ring, struct sk_buff *skb,
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u32 tx_flags, u8 *hdr_len);
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extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
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extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
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union ixgbe_adv_rx_desc *rx_desc,
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struct sk_buff *skb);
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extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
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struct scatterlist *sgl, unsigned int sgc);
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extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
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struct scatterlist *sgl, unsigned int sgc);
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extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
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extern int ixgbe_fcoe_enable(struct net_device *netdev);
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extern int ixgbe_fcoe_disable(struct net_device *netdev);
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#ifdef CONFIG_IXGBE_DCB
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extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
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extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
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#endif /* CONFIG_IXGBE_DCB */
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extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
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#endif /* IXGBE_FCOE */
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#endif /* _IXGBE_H_ */
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