131 lines
4.0 KiB
C
131 lines
4.0 KiB
C
/* $Id: cache.h,v 1.9 1999/08/14 03:51:58 anton Exp $
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* cache.h: Cache specific code for the Sparc. These include flushing
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* and direct tag/data line access.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC_CACHE_H
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#define _SPARC_CACHE_H
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#include <asm/asi.h>
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_BYTES 32
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#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
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#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */
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#define SMP_CACHE_BYTES 32
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/* Direct access to the instruction cache is provided through and
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* alternate address space. The IDC bit must be off in the ICCR on
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* HyperSparcs for these accesses to work. The code below does not do
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* any checking, the caller must do so. These routines are for
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* diagnostics only, but could end up being useful. Use with care.
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* Also, you are asking for trouble if you execute these in one of the
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* three instructions following a %asr/%psr access or modification.
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*/
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/* First, cache-tag access. */
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extern __inline__ unsigned int get_icache_tag(int setnum, int tagnum)
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{
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unsigned int vaddr, retval;
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vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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"=r" (retval) :
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"r" (vaddr), "i" (ASI_M_TXTC_TAG));
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return retval;
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}
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extern __inline__ void put_icache_tag(int setnum, int tagnum, unsigned int entry)
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{
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unsigned int vaddr;
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vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
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__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
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"r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
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"memory");
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}
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/* Second cache-data access. The data is returned two-32bit quantities
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* at a time.
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*/
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extern __inline__ void get_icache_data(int setnum, int tagnum, int subblock,
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unsigned int *data)
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{
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unsigned int value1, value2, vaddr;
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vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
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((subblock&0x3) << 3);
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__asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
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"or %%g0, %%g2, %0\n\t"
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"or %%g0, %%g3, %1\n\t" :
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"=r" (value1), "=r" (value2) :
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"r" (vaddr), "i" (ASI_M_TXTC_DATA) :
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"g2", "g3");
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data[0] = value1; data[1] = value2;
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}
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extern __inline__ void put_icache_data(int setnum, int tagnum, int subblock,
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unsigned int *data)
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{
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unsigned int value1, value2, vaddr;
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vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
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((subblock&0x3) << 3);
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value1 = data[0]; value2 = data[1];
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__asm__ __volatile__("or %%g0, %0, %%g2\n\t"
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"or %%g0, %1, %%g3\n\t"
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"stda %%g2, [%2] %3\n\t" : :
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"r" (value1), "r" (value2),
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"r" (vaddr), "i" (ASI_M_TXTC_DATA) :
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"g2", "g3", "memory" /* no joke */);
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}
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/* Different types of flushes with the ICACHE. Some of the flushes
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* affect both the ICACHE and the external cache. Others only clear
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* the ICACHE entries on the cpu itself. V8's (most) allow
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* granularity of flushes on the packet (element in line), whole line,
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* and entire cache (ie. all lines) level. The ICACHE only flushes are
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* ROSS HyperSparc specific and are in ross.h
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*/
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/* Flushes which clear out both the on-chip and external caches */
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extern __inline__ void flush_ei_page(unsigned int addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
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"r" (addr), "i" (ASI_M_FLUSH_PAGE) :
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"memory");
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}
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extern __inline__ void flush_ei_seg(unsigned int addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
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"r" (addr), "i" (ASI_M_FLUSH_SEG) :
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"memory");
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}
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extern __inline__ void flush_ei_region(unsigned int addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
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"r" (addr), "i" (ASI_M_FLUSH_REGION) :
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"memory");
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}
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extern __inline__ void flush_ei_ctx(unsigned int addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
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"r" (addr), "i" (ASI_M_FLUSH_CTX) :
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"memory");
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}
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extern __inline__ void flush_ei_user(unsigned int addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
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"r" (addr), "i" (ASI_M_FLUSH_USER) :
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"memory");
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}
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#endif /* !(_SPARC_CACHE_H) */
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