321 lines
7.7 KiB
ArmAsm
321 lines
7.7 KiB
ArmAsm
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright SUSE Linux Products GmbH 2009
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#include <asm/ppc_asm.h>
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#include <asm/kvm_asm.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/asm-offsets.h>
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#include <asm/exception-64s.h>
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#if defined(CONFIG_PPC_BOOK3S_64)
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#define ULONG_SIZE 8
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#define FUNC(name) GLUE(.,name)
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#define GET_SHADOW_VCPU(reg) \
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addi reg, r13, PACA_KVM_SVCPU
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#define DISABLE_INTERRUPTS \
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mfmsr r0; \
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rldicl r0,r0,48,1; \
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rotldi r0,r0,16; \
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mtmsrd r0,1; \
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#elif defined(CONFIG_PPC_BOOK3S_32)
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#define ULONG_SIZE 4
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#define FUNC(name) name
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#define GET_SHADOW_VCPU(reg) \
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lwz reg, (THREAD + THREAD_KVM_SVCPU)(r2)
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#define DISABLE_INTERRUPTS \
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mfmsr r0; \
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rlwinm r0,r0,0,17,15; \
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mtmsr r0; \
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#endif /* CONFIG_PPC_BOOK3S_XX */
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#define VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
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#define VCPU_LOAD_NVGPRS(vcpu) \
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PPC_LL r14, VCPU_GPR(r14)(vcpu); \
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PPC_LL r15, VCPU_GPR(r15)(vcpu); \
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PPC_LL r16, VCPU_GPR(r16)(vcpu); \
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PPC_LL r17, VCPU_GPR(r17)(vcpu); \
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PPC_LL r18, VCPU_GPR(r18)(vcpu); \
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PPC_LL r19, VCPU_GPR(r19)(vcpu); \
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PPC_LL r20, VCPU_GPR(r20)(vcpu); \
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PPC_LL r21, VCPU_GPR(r21)(vcpu); \
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PPC_LL r22, VCPU_GPR(r22)(vcpu); \
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PPC_LL r23, VCPU_GPR(r23)(vcpu); \
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PPC_LL r24, VCPU_GPR(r24)(vcpu); \
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PPC_LL r25, VCPU_GPR(r25)(vcpu); \
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PPC_LL r26, VCPU_GPR(r26)(vcpu); \
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PPC_LL r27, VCPU_GPR(r27)(vcpu); \
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PPC_LL r28, VCPU_GPR(r28)(vcpu); \
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PPC_LL r29, VCPU_GPR(r29)(vcpu); \
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PPC_LL r30, VCPU_GPR(r30)(vcpu); \
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PPC_LL r31, VCPU_GPR(r31)(vcpu); \
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/*****************************************************************************
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* *
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* Guest entry / exit code that is in kernel module memory (highmem) *
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* *
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****************************************************************************/
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/* Registers:
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* r3: kvm_run pointer
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* r4: vcpu pointer
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*/
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_GLOBAL(__kvmppc_vcpu_entry)
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kvm_start_entry:
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/* Write correct stack frame */
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mflr r0
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PPC_STL r0,PPC_LR_STKOFF(r1)
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/* Save host state to the stack */
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PPC_STLU r1, -SWITCH_FRAME_SIZE(r1)
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/* Save r3 (kvm_run) and r4 (vcpu) */
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SAVE_2GPRS(3, r1)
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/* Save non-volatile registers (r14 - r31) */
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SAVE_NVGPRS(r1)
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/* Save LR */
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PPC_STL r0, _LINK(r1)
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/* Load non-volatile guest state from the vcpu */
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VCPU_LOAD_NVGPRS(r4)
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GET_SHADOW_VCPU(r5)
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/* Save R1/R2 in the PACA */
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PPC_STL r1, SVCPU_HOST_R1(r5)
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PPC_STL r2, SVCPU_HOST_R2(r5)
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/* XXX swap in/out on load? */
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PPC_LL r3, VCPU_HIGHMEM_HANDLER(r4)
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PPC_STL r3, SVCPU_VMHANDLER(r5)
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kvm_start_lightweight:
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PPC_LL r10, VCPU_SHADOW_MSR(r4) /* r10 = vcpu->arch.shadow_msr */
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DISABLE_INTERRUPTS
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#ifdef CONFIG_PPC_BOOK3S_64
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/* Some guests may need to have dcbz set to 32 byte length.
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*
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* Usually we ensure that by patching the guest's instructions
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* to trap on dcbz and emulate it in the hypervisor.
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*
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* If we can, we should tell the CPU to use 32 byte dcbz though,
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* because that's a lot faster.
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*/
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PPC_LL r3, VCPU_HFLAGS(r4)
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rldicl. r3, r3, 0, 63 /* CR = ((r3 & 1) == 0) */
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beq no_dcbz32_on
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mfspr r3,SPRN_HID5
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ori r3, r3, 0x80 /* XXX HID5_dcbz32 = 0x80 */
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mtspr SPRN_HID5,r3
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no_dcbz32_on:
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#endif /* CONFIG_PPC_BOOK3S_64 */
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PPC_LL r6, VCPU_RMCALL(r4)
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mtctr r6
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PPC_LL r3, VCPU_TRAMPOLINE_ENTER(r4)
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LOAD_REG_IMMEDIATE(r4, MSR_KERNEL & ~(MSR_IR | MSR_DR))
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/* Jump to segment patching handler and into our guest */
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bctr
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/*
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* This is the handler in module memory. It gets jumped at from the
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* lowmem trampoline code, so it's basically the guest exit code.
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*
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*/
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.global kvmppc_handler_highmem
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kvmppc_handler_highmem:
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/*
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* Register usage at this point:
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*
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* R1 = host R1
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* R2 = host R2
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* R12 = exit handler id
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* R13 = PACA
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* SVCPU.* = guest *
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*
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*/
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/* R7 = vcpu */
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PPC_LL r7, GPR4(r1)
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#ifdef CONFIG_PPC_BOOK3S_64
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PPC_LL r5, VCPU_HFLAGS(r7)
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rldicl. r5, r5, 0, 63 /* CR = ((r5 & 1) == 0) */
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beq no_dcbz32_off
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li r4, 0
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mfspr r5,SPRN_HID5
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rldimi r5,r4,6,56
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mtspr SPRN_HID5,r5
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no_dcbz32_off:
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#endif /* CONFIG_PPC_BOOK3S_64 */
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PPC_STL r14, VCPU_GPR(r14)(r7)
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PPC_STL r15, VCPU_GPR(r15)(r7)
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PPC_STL r16, VCPU_GPR(r16)(r7)
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PPC_STL r17, VCPU_GPR(r17)(r7)
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PPC_STL r18, VCPU_GPR(r18)(r7)
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PPC_STL r19, VCPU_GPR(r19)(r7)
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PPC_STL r20, VCPU_GPR(r20)(r7)
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PPC_STL r21, VCPU_GPR(r21)(r7)
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PPC_STL r22, VCPU_GPR(r22)(r7)
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PPC_STL r23, VCPU_GPR(r23)(r7)
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PPC_STL r24, VCPU_GPR(r24)(r7)
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PPC_STL r25, VCPU_GPR(r25)(r7)
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PPC_STL r26, VCPU_GPR(r26)(r7)
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PPC_STL r27, VCPU_GPR(r27)(r7)
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PPC_STL r28, VCPU_GPR(r28)(r7)
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PPC_STL r29, VCPU_GPR(r29)(r7)
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PPC_STL r30, VCPU_GPR(r30)(r7)
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PPC_STL r31, VCPU_GPR(r31)(r7)
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/* Restore host msr -> SRR1 */
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PPC_LL r6, VCPU_HOST_MSR(r7)
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/*
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* For some interrupts, we need to call the real Linux
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* handler, so it can do work for us. This has to happen
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* as if the interrupt arrived from the kernel though,
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* so let's fake it here where most state is restored.
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*
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* Call Linux for hardware interrupts/decrementer
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* r3 = address of interrupt handler (exit reason)
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*/
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cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
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beq call_linux_handler
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cmpwi r12, BOOK3S_INTERRUPT_DECREMENTER
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beq call_linux_handler
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cmpwi r12, BOOK3S_INTERRUPT_PERFMON
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beq call_linux_handler
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/* Back to EE=1 */
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mtmsr r6
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sync
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b kvm_return_point
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call_linux_handler:
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/*
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* If we land here we need to jump back to the handler we
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* came from.
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*
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* We have a page that we can access from real mode, so let's
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* jump back to that and use it as a trampoline to get back into the
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* interrupt handler!
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*
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* R3 still contains the exit code,
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* R5 VCPU_HOST_RETIP and
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* R6 VCPU_HOST_MSR
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*/
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/* Restore host IP -> SRR0 */
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PPC_LL r5, VCPU_HOST_RETIP(r7)
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/* XXX Better move to a safe function?
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* What if we get an HTAB flush in between mtsrr0 and mtsrr1? */
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mtlr r12
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PPC_LL r4, VCPU_TRAMPOLINE_LOWMEM(r7)
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mtsrr0 r4
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LOAD_REG_IMMEDIATE(r3, MSR_KERNEL & ~(MSR_IR | MSR_DR))
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mtsrr1 r3
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RFI
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.global kvm_return_point
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kvm_return_point:
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/* Jump back to lightweight entry if we're supposed to */
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/* go back into the guest */
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/* Pass the exit number as 3rd argument to kvmppc_handle_exit */
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mr r5, r12
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/* Restore r3 (kvm_run) and r4 (vcpu) */
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REST_2GPRS(3, r1)
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bl FUNC(kvmppc_handle_exit)
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/* If RESUME_GUEST, get back in the loop */
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cmpwi r3, RESUME_GUEST
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beq kvm_loop_lightweight
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cmpwi r3, RESUME_GUEST_NV
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beq kvm_loop_heavyweight
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kvm_exit_loop:
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PPC_LL r4, _LINK(r1)
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mtlr r4
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/* Restore non-volatile host registers (r14 - r31) */
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REST_NVGPRS(r1)
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addi r1, r1, SWITCH_FRAME_SIZE
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blr
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kvm_loop_heavyweight:
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PPC_LL r4, _LINK(r1)
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PPC_STL r4, (PPC_LR_STKOFF + SWITCH_FRAME_SIZE)(r1)
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/* Load vcpu and cpu_run */
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REST_2GPRS(3, r1)
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/* Load non-volatile guest state from the vcpu */
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VCPU_LOAD_NVGPRS(r4)
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/* Jump back into the beginning of this function */
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b kvm_start_lightweight
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kvm_loop_lightweight:
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/* We'll need the vcpu pointer */
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REST_GPR(4, r1)
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/* Jump back into the beginning of this function */
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b kvm_start_lightweight
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