427 lines
11 KiB
C
427 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* (C) 2005, 2006 Red Hat Inc.
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*
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* Author: David Woodhouse <dwmw2@infradead.org>
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* Tom Sylla <tom.sylla@amd.com>
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*
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* Overview:
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* This is a device driver for the NAND flash controller found on
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* the AMD CS5535/CS5536 companion chipsets for the Geode processor.
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* mtd-id for command line partitioning is cs553x_nand_cs[0-3]
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* where 0-3 reflects the chip select for NAND.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/iopoll.h>
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#include <asm/msr.h>
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#define NR_CS553X_CONTROLLERS 4
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#define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */
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#define CAP_CS5535 0x2df000ULL
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#define CAP_CS5536 0x5df500ULL
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/* NAND Timing MSRs */
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#define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
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#define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
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#define MSR_NANDF_RSVD 0x5140001d /* Reserved */
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/* NAND BAR MSRs */
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#define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
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#define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
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#define MSR_DIVIL_LBAR_FLSH2 0x51400012 /* Flash Chip Select 2 */
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#define MSR_DIVIL_LBAR_FLSH3 0x51400013 /* Flash Chip Select 3 */
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/* Each made up of... */
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#define FLSH_LBAR_EN (1ULL<<32)
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#define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */
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#define FLSH_MEM_IO (1ULL<<34) /* 1 for MMIO */
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/* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
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/* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
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/* Pin function selection MSR (IDE vs. flash on the IDE pins) */
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#define MSR_DIVIL_BALL_OPTS 0x51400015
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#define PIN_OPT_IDE (1<<0) /* 0 for flash, 1 for IDE */
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/* Registers within the NAND flash controller BAR -- memory mapped */
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#define MM_NAND_DATA 0x00 /* 0 to 0x7ff, in fact */
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#define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */
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#define MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */
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#define MM_NAND_STS 0x810
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#define MM_NAND_ECC_LSB 0x811
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#define MM_NAND_ECC_MSB 0x812
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#define MM_NAND_ECC_COL 0x813
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#define MM_NAND_LAC 0x814
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#define MM_NAND_ECC_CTL 0x815
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/* Registers within the NAND flash controller BAR -- I/O mapped */
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#define IO_NAND_DATA 0x00 /* 0 to 3, in fact */
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#define IO_NAND_CTL 0x04
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#define IO_NAND_IO 0x05
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#define IO_NAND_STS 0x06
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#define IO_NAND_ECC_CTL 0x08
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#define IO_NAND_ECC_LSB 0x09
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#define IO_NAND_ECC_MSB 0x0a
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#define IO_NAND_ECC_COL 0x0b
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#define IO_NAND_LAC 0x0c
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#define CS_NAND_CTL_DIST_EN (1<<4) /* Enable NAND Distract interrupt */
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#define CS_NAND_CTL_RDY_INT_MASK (1<<3) /* Enable RDY/BUSY# interrupt */
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#define CS_NAND_CTL_ALE (1<<2)
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#define CS_NAND_CTL_CLE (1<<1)
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#define CS_NAND_CTL_CE (1<<0) /* Keep low; 1 to reset */
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#define CS_NAND_STS_FLASH_RDY (1<<3)
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#define CS_NAND_CTLR_BUSY (1<<2)
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#define CS_NAND_CMD_COMP (1<<1)
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#define CS_NAND_DIST_ST (1<<0)
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#define CS_NAND_ECC_PARITY (1<<2)
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#define CS_NAND_ECC_CLRECC (1<<1)
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#define CS_NAND_ECC_ENECC (1<<0)
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struct cs553x_nand_controller {
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struct nand_controller base;
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struct nand_chip chip;
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void __iomem *mmio;
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};
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static struct cs553x_nand_controller *
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to_cs553x(struct nand_controller *controller)
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{
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return container_of(controller, struct cs553x_nand_controller, base);
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}
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static int cs553x_write_ctrl_byte(struct cs553x_nand_controller *cs553x,
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u32 ctl, u8 data)
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{
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u8 status;
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int ret;
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writeb(ctl, cs553x->mmio + MM_NAND_CTL);
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writeb(data, cs553x->mmio + MM_NAND_IO);
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ret = readb_poll_timeout_atomic(cs553x->mmio + MM_NAND_STS, status,
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!(status & CS_NAND_CTLR_BUSY), 1,
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100000);
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if (ret)
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return ret;
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return 0;
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}
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static void cs553x_data_in(struct cs553x_nand_controller *cs553x, void *buf,
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unsigned int len)
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{
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writeb(0, cs553x->mmio + MM_NAND_CTL);
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while (unlikely(len > 0x800)) {
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memcpy_fromio(buf, cs553x->mmio, 0x800);
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buf += 0x800;
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len -= 0x800;
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}
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memcpy_fromio(buf, cs553x->mmio, len);
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}
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static void cs553x_data_out(struct cs553x_nand_controller *cs553x,
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const void *buf, unsigned int len)
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{
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writeb(0, cs553x->mmio + MM_NAND_CTL);
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while (unlikely(len > 0x800)) {
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memcpy_toio(cs553x->mmio, buf, 0x800);
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buf += 0x800;
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len -= 0x800;
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}
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memcpy_toio(cs553x->mmio, buf, len);
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}
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static int cs553x_wait_ready(struct cs553x_nand_controller *cs553x,
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unsigned int timeout_ms)
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{
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u8 mask = CS_NAND_CTLR_BUSY | CS_NAND_STS_FLASH_RDY;
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u8 status;
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return readb_poll_timeout(cs553x->mmio + MM_NAND_STS, status,
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(status & mask) == CS_NAND_STS_FLASH_RDY, 100,
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timeout_ms * 1000);
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}
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static int cs553x_exec_instr(struct cs553x_nand_controller *cs553x,
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const struct nand_op_instr *instr)
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{
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unsigned int i;
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int ret = 0;
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switch (instr->type) {
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case NAND_OP_CMD_INSTR:
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ret = cs553x_write_ctrl_byte(cs553x, CS_NAND_CTL_CLE,
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instr->ctx.cmd.opcode);
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break;
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case NAND_OP_ADDR_INSTR:
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for (i = 0; i < instr->ctx.addr.naddrs; i++) {
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ret = cs553x_write_ctrl_byte(cs553x, CS_NAND_CTL_ALE,
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instr->ctx.addr.addrs[i]);
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if (ret)
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break;
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}
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break;
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case NAND_OP_DATA_IN_INSTR:
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cs553x_data_in(cs553x, instr->ctx.data.buf.in,
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instr->ctx.data.len);
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break;
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case NAND_OP_DATA_OUT_INSTR:
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cs553x_data_out(cs553x, instr->ctx.data.buf.out,
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instr->ctx.data.len);
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break;
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case NAND_OP_WAITRDY_INSTR:
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ret = cs553x_wait_ready(cs553x, instr->ctx.waitrdy.timeout_ms);
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break;
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}
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if (instr->delay_ns)
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ndelay(instr->delay_ns);
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return ret;
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}
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static int cs553x_exec_op(struct nand_chip *this,
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const struct nand_operation *op,
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bool check_only)
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{
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struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
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unsigned int i;
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int ret;
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if (check_only)
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return true;
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/* De-assert the CE pin */
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writeb(0, cs553x->mmio + MM_NAND_CTL);
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for (i = 0; i < op->ninstrs; i++) {
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ret = cs553x_exec_instr(cs553x, &op->instrs[i]);
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if (ret)
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break;
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}
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/* Re-assert the CE pin. */
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writeb(CS_NAND_CTL_CE, cs553x->mmio + MM_NAND_CTL);
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return ret;
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}
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static void cs_enable_hwecc(struct nand_chip *this, int mode)
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{
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struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
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writeb(0x07, cs553x->mmio + MM_NAND_ECC_CTL);
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}
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static int cs_calculate_ecc(struct nand_chip *this, const u_char *dat,
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u_char *ecc_code)
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{
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struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
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uint32_t ecc;
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ecc = readl(cs553x->mmio + MM_NAND_STS);
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ecc_code[1] = ecc >> 8;
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ecc_code[0] = ecc >> 16;
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ecc_code[2] = ecc >> 24;
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return 0;
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}
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static struct cs553x_nand_controller *controllers[4];
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static int cs553x_attach_chip(struct nand_chip *chip)
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{
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if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
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return 0;
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chip->ecc.size = 256;
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chip->ecc.bytes = 3;
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chip->ecc.hwctl = cs_enable_hwecc;
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chip->ecc.calculate = cs_calculate_ecc;
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chip->ecc.correct = rawnand_sw_hamming_correct;
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chip->ecc.strength = 1;
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return 0;
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}
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static const struct nand_controller_ops cs553x_nand_controller_ops = {
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.exec_op = cs553x_exec_op,
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.attach_chip = cs553x_attach_chip,
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};
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static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
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{
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struct cs553x_nand_controller *controller;
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int err = 0;
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struct nand_chip *this;
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struct mtd_info *new_mtd;
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pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n",
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cs, mmio ? "MM" : "P", adr);
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if (!mmio) {
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pr_notice("PIO mode not yet implemented for CS553X NAND controller\n");
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return -ENXIO;
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}
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/* Allocate memory for MTD device structure and private data */
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controller = kzalloc(sizeof(*controller), GFP_KERNEL);
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if (!controller) {
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err = -ENOMEM;
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goto out;
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}
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this = &controller->chip;
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nand_controller_init(&controller->base);
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controller->base.ops = &cs553x_nand_controller_ops;
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this->controller = &controller->base;
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new_mtd = nand_to_mtd(this);
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/* Link the private data with the MTD structure */
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new_mtd->owner = THIS_MODULE;
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/* map physical address */
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controller->mmio = ioremap(adr, 4096);
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if (!controller->mmio) {
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pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);
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err = -EIO;
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goto out_mtd;
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}
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/* Enable the following for a flash based bad block table */
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this->bbt_options = NAND_BBT_USE_FLASH;
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new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);
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if (!new_mtd->name) {
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err = -ENOMEM;
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goto out_ior;
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}
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/* Scan to find existence of the device */
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err = nand_scan(this, 1);
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if (err)
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goto out_free;
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controllers[cs] = controller;
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goto out;
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out_free:
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kfree(new_mtd->name);
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out_ior:
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iounmap(controller->mmio);
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out_mtd:
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kfree(controller);
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out:
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return err;
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}
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static int is_geode(void)
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{
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/* These are the CPUs which will have a CS553[56] companion chip */
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
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boot_cpu_data.x86 == 5 &&
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boot_cpu_data.x86_model == 10)
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return 1; /* Geode LX */
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if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC ||
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boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) &&
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boot_cpu_data.x86 == 5 &&
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boot_cpu_data.x86_model == 5)
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return 1; /* Geode GX (née GX2) */
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return 0;
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}
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static int __init cs553x_init(void)
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{
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int err = -ENXIO;
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int i;
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uint64_t val;
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/* If the CPU isn't a Geode GX or LX, abort */
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if (!is_geode())
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return -ENXIO;
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/* If it doesn't have the CS553[56], abort */
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rdmsrl(MSR_DIVIL_GLD_CAP, val);
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val &= ~0xFFULL;
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if (val != CAP_CS5535 && val != CAP_CS5536)
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return -ENXIO;
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/* If it doesn't have the NAND controller enabled, abort */
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rdmsrl(MSR_DIVIL_BALL_OPTS, val);
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if (val & PIN_OPT_IDE) {
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pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
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return -ENXIO;
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}
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for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
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rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
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if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
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err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
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}
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/* Register all devices together here. This means we can easily hack it to
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do mtdconcat etc. if we want to. */
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for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
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if (controllers[i]) {
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/* If any devices registered, return success. Else the last error. */
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mtd_device_register(nand_to_mtd(&controllers[i]->chip),
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NULL, 0);
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err = 0;
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}
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}
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return err;
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}
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module_init(cs553x_init);
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static void __exit cs553x_cleanup(void)
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{
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int i;
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for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
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struct cs553x_nand_controller *controller = controllers[i];
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struct nand_chip *this = &controller->chip;
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struct mtd_info *mtd = nand_to_mtd(this);
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int ret;
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if (!mtd)
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continue;
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/* Release resources, unregister device */
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ret = mtd_device_unregister(mtd);
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WARN_ON(ret);
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nand_cleanup(this);
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kfree(mtd->name);
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controllers[i] = NULL;
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/* unmap physical address */
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iounmap(controller->mmio);
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/* Free the MTD device structure */
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kfree(controller);
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}
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}
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module_exit(cs553x_cleanup);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
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MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");
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