687 lines
22 KiB
C
687 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* xHCI host controller driver PCI Bus Glue.
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*/
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/acpi.h>
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#include <linux/reset.h>
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#include "xhci.h"
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#include "xhci-trace.h"
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#include "xhci-pci.h"
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#define SSIC_PORT_NUM 2
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#define SSIC_PORT_CFG2 0x880c
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#define SSIC_PORT_CFG2_OFFSET 0x30
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#define PROG_DONE (1 << 30)
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#define SSIC_PORT_UNUSED (1 << 31)
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#define SPARSE_DISABLE_BIT 17
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#define SPARSE_CNTL_ENABLE 0xC12C
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/* Device for a quirk */
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#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
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#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
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#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
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#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
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#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
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#define PCI_VENDOR_ID_ETRON 0x1b6f
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#define PCI_DEVICE_ID_EJ168 0x7023
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
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#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
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#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
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#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
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#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
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#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
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#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
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#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
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#define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
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#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
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#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
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#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e
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#define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
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#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
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#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
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#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
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#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
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#define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
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#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
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#define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
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#define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
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#define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
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static const char hcd_name[] = "xhci_hcd";
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static struct hc_driver __read_mostly xhci_pci_hc_driver;
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static int xhci_pci_setup(struct usb_hcd *hcd);
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static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
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.reset = xhci_pci_setup,
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};
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/* called after powerup, by probe or system-pm "wakeup" */
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static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
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{
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/*
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* TODO: Implement finding debug ports later.
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* TODO: see if there are any quirks that need to be added to handle
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* new extended capabilities.
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*/
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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if (!pci_set_mwi(pdev))
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xhci_dbg(xhci, "MWI active\n");
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xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
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return 0;
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}
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static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct xhci_driver_data *driver_data;
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const struct pci_device_id *id;
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id = pci_match_id(pdev->driver->id_table, pdev);
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if (id && id->driver_data) {
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driver_data = (struct xhci_driver_data *)id->driver_data;
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xhci->quirks |= driver_data->quirks;
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}
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/* Look for vendor-specific quirks */
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if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
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(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
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pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 ||
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pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
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if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
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pdev->revision == 0x0) {
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xhci->quirks |= XHCI_RESET_EP_QUIRK;
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Fresco Logic xHC needs configure"
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" endpoint cmd after reset endpoint");
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}
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if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
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pdev->revision == 0x4) {
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xhci->quirks |= XHCI_SLOW_SUSPEND;
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Fresco Logic xHC revision %u"
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"must be suspended extra slowly",
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pdev->revision);
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}
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if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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/* Fresco Logic confirms: all revisions of this chip do not
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* support MSI, even though some of them claim to in their PCI
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* capabilities.
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*/
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xhci->quirks |= XHCI_BROKEN_MSI;
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Fresco Logic revision %u "
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"has broken MSI implementation",
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pdev->revision);
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xhci->quirks |= XHCI_TRUST_TX_LENGTH;
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}
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if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
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pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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if (pdev->vendor == PCI_VENDOR_ID_NEC)
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xhci->quirks |= XHCI_NEC_HOST;
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if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
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xhci->quirks |= XHCI_AMD_0x96_HOST;
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/* AMD PLL quirk */
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if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
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xhci->quirks |= XHCI_AMD_PLL_FIX;
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if (pdev->vendor == PCI_VENDOR_ID_AMD &&
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(pdev->device == 0x145c ||
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pdev->device == 0x15e0 ||
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pdev->device == 0x15e1 ||
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pdev->device == 0x43bb))
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xhci->quirks |= XHCI_SUSPEND_DELAY;
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if (pdev->vendor == PCI_VENDOR_ID_AMD &&
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(pdev->device == 0x15e0 || pdev->device == 0x15e1))
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xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
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if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
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xhci->quirks |= XHCI_DISABLE_SPARSE;
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xhci->quirks |= XHCI_RESET_ON_RESUME;
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}
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if (pdev->vendor == PCI_VENDOR_ID_AMD)
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xhci->quirks |= XHCI_TRUST_TX_LENGTH;
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if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
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((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
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(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
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(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
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(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
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xhci->quirks |= XHCI_U2_DISABLE_WAKE;
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if (pdev->vendor == PCI_VENDOR_ID_AMD &&
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pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
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xhci->quirks |= XHCI_BROKEN_D3COLD;
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if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
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xhci->quirks |= XHCI_LPM_SUPPORT;
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xhci->quirks |= XHCI_INTEL_HOST;
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xhci->quirks |= XHCI_AVOID_BEI;
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}
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
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xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
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xhci->limit_active_eps = 64;
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xhci->quirks |= XHCI_SW_BW_CHECKING;
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/*
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* PPT desktop boards DH77EB and DH77DF will power back on after
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* a few seconds of being shutdown. The fix for this is to
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* switch the ports from xHCI to EHCI on shutdown. We can't use
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* DMI information to find those particular boards (since each
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* vendor will change the board name), so we have to key off all
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* PPT chipsets.
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*/
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xhci->quirks |= XHCI_SPURIOUS_REBOOT;
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}
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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(pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
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xhci->quirks |= XHCI_SPURIOUS_REBOOT;
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xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
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}
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
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xhci->quirks |= XHCI_PME_STUCK_QUIRK;
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}
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
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xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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(pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
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xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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(pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
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xhci->quirks |= XHCI_MISSING_CAS;
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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(pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
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xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
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if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
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pdev->device == PCI_DEVICE_ID_EJ168) {
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xhci->quirks |= XHCI_RESET_ON_RESUME;
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xhci->quirks |= XHCI_TRUST_TX_LENGTH;
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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}
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if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
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pdev->device == 0x0014) {
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xhci->quirks |= XHCI_TRUST_TX_LENGTH;
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xhci->quirks |= XHCI_ZERO_64B_REGS;
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}
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if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
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pdev->device == 0x0015) {
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xhci->quirks |= XHCI_RESET_ON_RESUME;
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xhci->quirks |= XHCI_ZERO_64B_REGS;
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}
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if (pdev->vendor == PCI_VENDOR_ID_VIA)
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xhci->quirks |= XHCI_RESET_ON_RESUME;
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/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
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if (pdev->vendor == PCI_VENDOR_ID_VIA &&
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pdev->device == 0x3432)
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
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xhci->quirks |= XHCI_LPM_SUPPORT;
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xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
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}
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if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
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pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
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pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
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xhci->quirks |= XHCI_TRUST_TX_LENGTH;
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xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
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}
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if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
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(pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
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pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
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pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
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xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
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if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
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pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
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xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
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if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
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xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
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if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
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pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
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pdev->device == 0x9026)
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xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
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if (pdev->vendor == PCI_VENDOR_ID_AMD &&
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(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
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pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
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xhci->quirks |= XHCI_NO_SOFT_RETRY;
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if (xhci->quirks & XHCI_RESET_ON_RESUME)
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Resetting on resume");
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}
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#ifdef CONFIG_ACPI
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static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
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{
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static const guid_t intel_dsm_guid =
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GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
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0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
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union acpi_object *obj;
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obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
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NULL);
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ACPI_FREE(obj);
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}
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#else
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static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
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#endif /* CONFIG_ACPI */
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/* called during probe() after chip reset completes */
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static int xhci_pci_setup(struct usb_hcd *hcd)
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{
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struct xhci_hcd *xhci;
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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int retval;
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xhci = hcd_to_xhci(hcd);
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if (!xhci->sbrn)
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pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
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/* imod_interval is the interrupt moderation value in nanoseconds. */
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xhci->imod_interval = 40000;
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retval = xhci_gen_setup(hcd, xhci_pci_quirks);
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if (retval)
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return retval;
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if (!usb_hcd_is_primary_hcd(hcd))
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return 0;
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if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
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xhci_pme_acpi_rtd3_enable(pdev);
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xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
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/* Find any debug ports */
|
|
return xhci_pci_reinit(xhci, pdev);
|
|
}
|
|
|
|
/*
|
|
* We need to register our own PCI probe function (instead of the USB core's
|
|
* function) in order to create a second roothub under xHCI.
|
|
*/
|
|
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
int retval;
|
|
struct xhci_hcd *xhci;
|
|
struct usb_hcd *hcd;
|
|
struct xhci_driver_data *driver_data;
|
|
struct reset_control *reset;
|
|
|
|
driver_data = (struct xhci_driver_data *)id->driver_data;
|
|
if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
|
|
retval = renesas_xhci_check_request_fw(dev, id);
|
|
if (retval)
|
|
return retval;
|
|
}
|
|
|
|
reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
|
|
if (IS_ERR(reset))
|
|
return PTR_ERR(reset);
|
|
reset_control_reset(reset);
|
|
|
|
/* Prevent runtime suspending between USB-2 and USB-3 initialization */
|
|
pm_runtime_get_noresume(&dev->dev);
|
|
|
|
/* Register the USB 2.0 roothub.
|
|
* FIXME: USB core must know to register the USB 2.0 roothub first.
|
|
* This is sort of silly, because we could just set the HCD driver flags
|
|
* to say USB 2.0, but I'm not sure what the implications would be in
|
|
* the other parts of the HCD code.
|
|
*/
|
|
retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
|
|
|
|
if (retval)
|
|
goto put_runtime_pm;
|
|
|
|
/* USB 2.0 roothub is stored in the PCI device now. */
|
|
hcd = dev_get_drvdata(&dev->dev);
|
|
xhci = hcd_to_xhci(hcd);
|
|
xhci->reset = reset;
|
|
xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
|
|
pci_name(dev), hcd);
|
|
if (!xhci->shared_hcd) {
|
|
retval = -ENOMEM;
|
|
goto dealloc_usb2_hcd;
|
|
}
|
|
|
|
retval = xhci_ext_cap_init(xhci);
|
|
if (retval)
|
|
goto put_usb3_hcd;
|
|
|
|
retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
|
|
IRQF_SHARED);
|
|
if (retval)
|
|
goto put_usb3_hcd;
|
|
/* Roothub already marked as USB 3.0 speed */
|
|
|
|
if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
|
|
HCC_MAX_PSA(xhci->hcc_params) >= 4)
|
|
xhci->shared_hcd->can_do_streams = 1;
|
|
|
|
/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
|
|
pm_runtime_put_noidle(&dev->dev);
|
|
|
|
if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
|
|
pm_runtime_allow(&dev->dev);
|
|
|
|
return 0;
|
|
|
|
put_usb3_hcd:
|
|
usb_put_hcd(xhci->shared_hcd);
|
|
dealloc_usb2_hcd:
|
|
usb_hcd_pci_remove(dev);
|
|
put_runtime_pm:
|
|
pm_runtime_put_noidle(&dev->dev);
|
|
return retval;
|
|
}
|
|
|
|
static void xhci_pci_remove(struct pci_dev *dev)
|
|
{
|
|
struct xhci_hcd *xhci;
|
|
|
|
xhci = hcd_to_xhci(pci_get_drvdata(dev));
|
|
|
|
xhci->xhc_state |= XHCI_STATE_REMOVING;
|
|
|
|
if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
|
|
pm_runtime_forbid(&dev->dev);
|
|
|
|
if (xhci->shared_hcd) {
|
|
usb_remove_hcd(xhci->shared_hcd);
|
|
usb_put_hcd(xhci->shared_hcd);
|
|
xhci->shared_hcd = NULL;
|
|
}
|
|
|
|
/* Workaround for spurious wakeups at shutdown with HSW */
|
|
if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
|
|
pci_set_power_state(dev, PCI_D3hot);
|
|
|
|
usb_hcd_pci_remove(dev);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
/*
|
|
* In some Intel xHCI controllers, in order to get D3 working,
|
|
* through a vendor specific SSIC CONFIG register at offset 0x883c,
|
|
* SSIC PORT need to be marked as "unused" before putting xHCI
|
|
* into D3. After D3 exit, the SSIC port need to be marked as "used".
|
|
* Without this change, xHCI might not enter D3 state.
|
|
*/
|
|
static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
u32 val;
|
|
void __iomem *reg;
|
|
int i;
|
|
|
|
for (i = 0; i < SSIC_PORT_NUM; i++) {
|
|
reg = (void __iomem *) xhci->cap_regs +
|
|
SSIC_PORT_CFG2 +
|
|
i * SSIC_PORT_CFG2_OFFSET;
|
|
|
|
/* Notify SSIC that SSIC profile programming is not done. */
|
|
val = readl(reg) & ~PROG_DONE;
|
|
writel(val, reg);
|
|
|
|
/* Mark SSIC port as unused(suspend) or used(resume) */
|
|
val = readl(reg);
|
|
if (suspend)
|
|
val |= SSIC_PORT_UNUSED;
|
|
else
|
|
val &= ~SSIC_PORT_UNUSED;
|
|
writel(val, reg);
|
|
|
|
/* Notify SSIC that SSIC profile programming is done */
|
|
val = readl(reg) | PROG_DONE;
|
|
writel(val, reg);
|
|
readl(reg);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Make sure PME works on some Intel xHCI controllers by writing 1 to clear
|
|
* the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
|
|
*/
|
|
static void xhci_pme_quirk(struct usb_hcd *hcd)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
void __iomem *reg;
|
|
u32 val;
|
|
|
|
reg = (void __iomem *) xhci->cap_regs + 0x80a4;
|
|
val = readl(reg);
|
|
writel(val | BIT(28), reg);
|
|
readl(reg);
|
|
}
|
|
|
|
static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
|
|
reg &= ~BIT(SPARSE_DISABLE_BIT);
|
|
writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
|
|
}
|
|
|
|
static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
|
|
int ret;
|
|
|
|
/*
|
|
* Systems with the TI redriver that loses port status change events
|
|
* need to have the registers polled during D3, so avoid D3cold.
|
|
*/
|
|
if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
|
|
pci_d3cold_disable(pdev);
|
|
|
|
if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
|
|
xhci_pme_quirk(hcd);
|
|
|
|
if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
|
|
xhci_ssic_port_unused_quirk(hcd, true);
|
|
|
|
if (xhci->quirks & XHCI_DISABLE_SPARSE)
|
|
xhci_sparse_control_quirk(hcd);
|
|
|
|
ret = xhci_suspend(xhci, do_wakeup);
|
|
if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
|
|
xhci_ssic_port_unused_quirk(hcd, false);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
|
|
int retval = 0;
|
|
|
|
reset_control_reset(xhci->reset);
|
|
|
|
/* The BIOS on systems with the Intel Panther Point chipset may or may
|
|
* not support xHCI natively. That means that during system resume, it
|
|
* may switch the ports back to EHCI so that users can use their
|
|
* keyboard to select a kernel from GRUB after resume from hibernate.
|
|
*
|
|
* The BIOS is supposed to remember whether the OS had xHCI ports
|
|
* enabled before resume, and switch the ports back to xHCI when the
|
|
* BIOS/OS semaphore is written, but we all know we can't trust BIOS
|
|
* writers.
|
|
*
|
|
* Unconditionally switch the ports back to xHCI after a system resume.
|
|
* It should not matter whether the EHCI or xHCI controller is
|
|
* resumed first. It's enough to do the switchover in xHCI because
|
|
* USB core won't notice anything as the hub driver doesn't start
|
|
* running again until after all the devices (including both EHCI and
|
|
* xHCI host controllers) have been resumed.
|
|
*/
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_INTEL)
|
|
usb_enable_intel_xhci_ports(pdev);
|
|
|
|
if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
|
|
xhci_ssic_port_unused_quirk(hcd, false);
|
|
|
|
if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
|
|
xhci_pme_quirk(hcd);
|
|
|
|
retval = xhci_resume(xhci, hibernated);
|
|
return retval;
|
|
}
|
|
|
|
static void xhci_pci_shutdown(struct usb_hcd *hcd)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
|
|
|
|
xhci_shutdown(hcd);
|
|
|
|
/* Yet another workaround for spurious wakeups at shutdown with HSW */
|
|
if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
|
|
pci_set_power_state(pdev, PCI_D3hot);
|
|
}
|
|
#endif /* CONFIG_PM */
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
static const struct xhci_driver_data reneses_data = {
|
|
.quirks = XHCI_RENESAS_FW_QUIRK,
|
|
.firmware = "renesas_usb_fw.mem",
|
|
};
|
|
|
|
/* PCI driver selection metadata; PCI hotplugging uses this */
|
|
static const struct pci_device_id pci_ids[] = {
|
|
{ PCI_DEVICE(0x1912, 0x0014),
|
|
.driver_data = (unsigned long)&reneses_data,
|
|
},
|
|
{ PCI_DEVICE(0x1912, 0x0015),
|
|
.driver_data = (unsigned long)&reneses_data,
|
|
},
|
|
/* handle any USB 3.0 xHCI controller */
|
|
{ PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
|
|
},
|
|
{ /* end: all zeroes */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, pci_ids);
|
|
|
|
/*
|
|
* Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
|
|
* load firmware, so don't encumber the xhci-pci driver with it.
|
|
*/
|
|
#if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
|
|
MODULE_FIRMWARE("renesas_usb_fw.mem");
|
|
#endif
|
|
|
|
/* pci driver glue; this is a "new style" PCI driver module */
|
|
static struct pci_driver xhci_pci_driver = {
|
|
.name = hcd_name,
|
|
.id_table = pci_ids,
|
|
|
|
.probe = xhci_pci_probe,
|
|
.remove = xhci_pci_remove,
|
|
/* suspend and resume implemented later */
|
|
|
|
.shutdown = usb_hcd_pci_shutdown,
|
|
#ifdef CONFIG_PM
|
|
.driver = {
|
|
.pm = &usb_hcd_pci_pm_ops
|
|
},
|
|
#endif
|
|
};
|
|
|
|
static int __init xhci_pci_init(void)
|
|
{
|
|
xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
|
|
#ifdef CONFIG_PM
|
|
xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
|
|
xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
|
|
xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
|
|
#endif
|
|
return pci_register_driver(&xhci_pci_driver);
|
|
}
|
|
module_init(xhci_pci_init);
|
|
|
|
static void __exit xhci_pci_exit(void)
|
|
{
|
|
pci_unregister_driver(&xhci_pci_driver);
|
|
}
|
|
module_exit(xhci_pci_exit);
|
|
|
|
MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
|
|
MODULE_LICENSE("GPL");
|