811 lines
20 KiB
C
811 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek xHCI Host Controller Driver
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*
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* Copyright (c) 2015 MediaTek Inc.
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* Author:
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* Chunfeng Yun <chunfeng.yun@mediatek.com>
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*/
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#include <linux/dma-mapping.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include "xhci.h"
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#include "xhci-mtk.h"
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/* ip_pw_ctrl0 register */
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#define CTRL0_IP_SW_RST BIT(0)
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/* ip_pw_ctrl1 register */
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#define CTRL1_IP_HOST_PDN BIT(0)
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/* ip_pw_ctrl2 register */
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#define CTRL2_IP_DEV_PDN BIT(0)
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/* ip_pw_sts1 register */
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#define STS1_IP_SLEEP_STS BIT(30)
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#define STS1_U3_MAC_RST BIT(16)
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#define STS1_XHCI_RST BIT(11)
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#define STS1_SYS125_RST BIT(10)
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#define STS1_REF_RST BIT(8)
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#define STS1_SYSPLL_STABLE BIT(0)
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/* ip_xhci_cap register */
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#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
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#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
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/* u3_ctrl_p register */
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#define CTRL_U3_PORT_HOST_SEL BIT(2)
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#define CTRL_U3_PORT_PDN BIT(1)
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#define CTRL_U3_PORT_DIS BIT(0)
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/* u2_ctrl_p register */
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#define CTRL_U2_PORT_HOST_SEL BIT(2)
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#define CTRL_U2_PORT_PDN BIT(1)
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#define CTRL_U2_PORT_DIS BIT(0)
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/* u2_phy_pll register */
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#define CTRL_U2_FORCE_PLL_STB BIT(28)
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/* xHCI CSR */
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#define LS_EOF_CFG 0x930
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#define LSEOF_OFFSET 0x89
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#define FS_EOF_CFG 0x934
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#define FSEOF_OFFSET 0x2e
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#define SS_GEN1_EOF_CFG 0x93c
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#define SSG1EOF_OFFSET 0x78
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#define HFCNTR_CFG 0x944
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#define ITP_DELTA_CLK (0xa << 1)
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#define ITP_DELTA_CLK_MASK GENMASK(5, 1)
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#define FRMCNT_LEV1_RANG (0x12b << 8)
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#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)
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#define SS_GEN2_EOF_CFG 0x990
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#define SSG2EOF_OFFSET 0x3c
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#define XSEOF_OFFSET_MASK GENMASK(11, 0)
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/* usb remote wakeup registers in syscon */
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/* mt8173 etc */
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#define PERI_WK_CTRL1 0x4
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#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
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#define WC1_IS_EN BIT(25)
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#define WC1_IS_P BIT(6) /* polarity for ip sleep */
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/* mt8183 */
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#define PERI_WK_CTRL0 0x0
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#define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */
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#define WC0_IS_P BIT(12) /* polarity */
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#define WC0_IS_EN BIT(6)
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/* mt8192 */
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#define WC0_SSUSB0_CDEN BIT(6)
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#define WC0_IS_SPM_EN BIT(1)
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/* mt2712 etc */
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#define PERI_SSUSB_SPM_CTRL 0x0
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#define SSC_IP_SLEEP_EN BIT(4)
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#define SSC_SPM_INT_EN BIT(1)
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enum ssusb_uwk_vers {
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SSUSB_UWK_V1 = 1,
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SSUSB_UWK_V2,
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SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
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SSUSB_UWK_V1_2, /* specific revision 1.2 */
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};
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/*
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* MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
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* is calculated from the frame counter clock 24M, but in fact, the clock
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* is 48M, add workaround for it.
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*/
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static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
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{
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struct device *dev = mtk->dev;
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struct usb_hcd *hcd = mtk->hcd;
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u32 value;
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if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
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return;
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value = readl(hcd->regs + HFCNTR_CFG);
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value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
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value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
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writel(value, hcd->regs + HFCNTR_CFG);
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value = readl(hcd->regs + LS_EOF_CFG);
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value &= ~XSEOF_OFFSET_MASK;
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value |= LSEOF_OFFSET;
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writel(value, hcd->regs + LS_EOF_CFG);
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value = readl(hcd->regs + FS_EOF_CFG);
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value &= ~XSEOF_OFFSET_MASK;
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value |= FSEOF_OFFSET;
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writel(value, hcd->regs + FS_EOF_CFG);
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value = readl(hcd->regs + SS_GEN1_EOF_CFG);
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value &= ~XSEOF_OFFSET_MASK;
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value |= SSG1EOF_OFFSET;
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writel(value, hcd->regs + SS_GEN1_EOF_CFG);
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value = readl(hcd->regs + SS_GEN2_EOF_CFG);
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value &= ~XSEOF_OFFSET_MASK;
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value |= SSG2EOF_OFFSET;
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writel(value, hcd->regs + SS_GEN2_EOF_CFG);
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}
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static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
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{
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struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
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u32 value, check_val;
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int u3_ports_disabled = 0;
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int ret;
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int i;
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if (!mtk->has_ippc)
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return 0;
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/* power on host ip */
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value = readl(&ippc->ip_pw_ctr1);
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value &= ~CTRL1_IP_HOST_PDN;
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writel(value, &ippc->ip_pw_ctr1);
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/* power on and enable u3 ports except skipped ones */
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for (i = 0; i < mtk->num_u3_ports; i++) {
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if ((0x1 << i) & mtk->u3p_dis_msk) {
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u3_ports_disabled++;
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continue;
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}
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value = readl(&ippc->u3_ctrl_p[i]);
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value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
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value |= CTRL_U3_PORT_HOST_SEL;
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writel(value, &ippc->u3_ctrl_p[i]);
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}
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/* power on and enable all u2 ports except skipped ones */
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for (i = 0; i < mtk->num_u2_ports; i++) {
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if (BIT(i) & mtk->u2p_dis_msk)
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continue;
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value = readl(&ippc->u2_ctrl_p[i]);
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value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
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value |= CTRL_U2_PORT_HOST_SEL;
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writel(value, &ippc->u2_ctrl_p[i]);
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}
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/*
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* wait for clocks to be stable, and clock domains reset to
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* be inactive after power on and enable ports
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*/
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check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
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STS1_SYS125_RST | STS1_XHCI_RST;
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if (mtk->num_u3_ports > u3_ports_disabled)
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check_val |= STS1_U3_MAC_RST;
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ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
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(check_val == (value & check_val)), 100, 20000);
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if (ret) {
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dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
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return ret;
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}
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return 0;
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}
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static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
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{
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struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
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u32 value;
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int ret;
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int i;
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if (!mtk->has_ippc)
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return 0;
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/* power down u3 ports except skipped ones */
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for (i = 0; i < mtk->num_u3_ports; i++) {
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if ((0x1 << i) & mtk->u3p_dis_msk)
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continue;
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value = readl(&ippc->u3_ctrl_p[i]);
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value |= CTRL_U3_PORT_PDN;
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writel(value, &ippc->u3_ctrl_p[i]);
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}
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/* power down all u2 ports except skipped ones */
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for (i = 0; i < mtk->num_u2_ports; i++) {
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if (BIT(i) & mtk->u2p_dis_msk)
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continue;
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value = readl(&ippc->u2_ctrl_p[i]);
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value |= CTRL_U2_PORT_PDN;
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writel(value, &ippc->u2_ctrl_p[i]);
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}
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/* power down host ip */
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value = readl(&ippc->ip_pw_ctr1);
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value |= CTRL1_IP_HOST_PDN;
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writel(value, &ippc->ip_pw_ctr1);
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/* wait for host ip to sleep */
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ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
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(value & STS1_IP_SLEEP_STS), 100, 100000);
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if (ret) {
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dev_err(mtk->dev, "ip sleep failed!!!\n");
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return ret;
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}
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return 0;
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}
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static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
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{
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struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
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u32 value;
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if (!mtk->has_ippc)
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return 0;
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/* reset whole ip */
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value = readl(&ippc->ip_pw_ctr0);
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value |= CTRL0_IP_SW_RST;
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writel(value, &ippc->ip_pw_ctr0);
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udelay(1);
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value = readl(&ippc->ip_pw_ctr0);
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value &= ~CTRL0_IP_SW_RST;
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writel(value, &ippc->ip_pw_ctr0);
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/*
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* device ip is default power-on in fact
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* power down device ip, otherwise ip-sleep will fail
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*/
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value = readl(&ippc->ip_pw_ctr2);
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value |= CTRL2_IP_DEV_PDN;
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writel(value, &ippc->ip_pw_ctr2);
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value = readl(&ippc->ip_xhci_cap);
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mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
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mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
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dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
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mtk->num_u2_ports, mtk->num_u3_ports);
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return xhci_mtk_host_enable(mtk);
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}
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/* only clocks can be turn off for ip-sleep wakeup mode */
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static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
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{
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u32 reg, msk, val;
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switch (mtk->uwk_vers) {
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case SSUSB_UWK_V1:
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reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
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msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
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val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
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break;
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case SSUSB_UWK_V1_1:
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reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
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msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
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val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0;
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break;
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case SSUSB_UWK_V1_2:
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reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
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msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
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val = enable ? msk : 0;
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break;
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case SSUSB_UWK_V2:
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reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
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msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
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val = enable ? msk : 0;
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break;
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default:
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return;
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}
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regmap_update_bits(mtk->uwk, reg, msk, val);
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}
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static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
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struct device_node *dn)
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{
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struct of_phandle_args args;
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int ret;
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/* Wakeup function is optional */
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mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
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if (!mtk->uwk_en)
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return 0;
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ret = of_parse_phandle_with_fixed_args(dn,
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"mediatek,syscon-wakeup", 2, 0, &args);
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if (ret)
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return ret;
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mtk->uwk_reg_base = args.args[0];
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mtk->uwk_vers = args.args[1];
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mtk->uwk = syscon_node_to_regmap(args.np);
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of_node_put(args.np);
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dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
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mtk->uwk_reg_base, mtk->uwk_vers);
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return PTR_ERR_OR_ZERO(mtk->uwk);
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}
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static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
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{
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if (mtk->uwk_en)
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usb_wakeup_ip_sleep_set(mtk, enable);
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}
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static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
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{
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struct clk_bulk_data *clks = mtk->clks;
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clks[0].id = "sys_ck";
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clks[1].id = "xhci_ck";
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clks[2].id = "ref_ck";
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clks[3].id = "mcu_ck";
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clks[4].id = "dma_ck";
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return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks);
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}
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static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
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{
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int ret;
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ret = regulator_enable(mtk->vbus);
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if (ret) {
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dev_err(mtk->dev, "failed to enable vbus\n");
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return ret;
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}
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ret = regulator_enable(mtk->vusb33);
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if (ret) {
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dev_err(mtk->dev, "failed to enable vusb33\n");
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regulator_disable(mtk->vbus);
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return ret;
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}
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return 0;
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}
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static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
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{
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regulator_disable(mtk->vbus);
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regulator_disable(mtk->vusb33);
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}
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static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
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{
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struct usb_hcd *hcd = xhci_to_hcd(xhci);
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struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
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/*
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* As of now platform drivers don't provide MSI support so we ensure
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* here that the generic code does not try to make a pci_dev from our
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* dev struct in order to setup MSI
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*/
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xhci->quirks |= XHCI_PLAT;
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xhci->quirks |= XHCI_MTK_HOST;
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/*
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* MTK host controller gives a spurious successful event after a
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* short transfer. Ignore it.
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*/
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xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
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if (mtk->lpm_support)
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xhci->quirks |= XHCI_LPM_SUPPORT;
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if (mtk->u2_lpm_disable)
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xhci->quirks |= XHCI_HW_LPM_DISABLE;
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/*
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* MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
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* and it's 3 when support it.
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*/
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if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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}
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/* called during probe() after chip reset completes */
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static int xhci_mtk_setup(struct usb_hcd *hcd)
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{
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struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
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int ret;
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if (usb_hcd_is_primary_hcd(hcd)) {
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ret = xhci_mtk_ssusb_config(mtk);
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if (ret)
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return ret;
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/* workaround only for mt8195 */
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xhci_mtk_set_frame_interval(mtk);
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}
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ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
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if (ret)
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return ret;
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if (usb_hcd_is_primary_hcd(hcd)) {
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ret = xhci_mtk_sch_init(mtk);
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if (ret)
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return ret;
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}
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return ret;
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}
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static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
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.reset = xhci_mtk_setup,
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.add_endpoint = xhci_mtk_add_ep,
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.drop_endpoint = xhci_mtk_drop_ep,
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.check_bandwidth = xhci_mtk_check_bandwidth,
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.reset_bandwidth = xhci_mtk_reset_bandwidth,
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};
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static struct hc_driver __read_mostly xhci_mtk_hc_driver;
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static int xhci_mtk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
|
|
struct device_node *node = dev->of_node;
|
|
struct xhci_hcd_mtk *mtk;
|
|
const struct hc_driver *driver;
|
|
struct xhci_hcd *xhci;
|
|
struct resource *res;
|
|
struct usb_hcd *hcd;
|
|
int ret = -ENODEV;
|
|
int wakeup_irq;
|
|
int irq;
|
|
|
|
if (usb_disabled())
|
|
return -ENODEV;
|
|
|
|
driver = &xhci_mtk_hc_driver;
|
|
mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
|
|
if (!mtk)
|
|
return -ENOMEM;
|
|
|
|
mtk->dev = dev;
|
|
mtk->vbus = devm_regulator_get(dev, "vbus");
|
|
if (IS_ERR(mtk->vbus)) {
|
|
dev_err(dev, "fail to get vbus\n");
|
|
return PTR_ERR(mtk->vbus);
|
|
}
|
|
|
|
mtk->vusb33 = devm_regulator_get(dev, "vusb33");
|
|
if (IS_ERR(mtk->vusb33)) {
|
|
dev_err(dev, "fail to get vusb33\n");
|
|
return PTR_ERR(mtk->vusb33);
|
|
}
|
|
|
|
ret = xhci_mtk_clks_get(mtk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
irq = platform_get_irq_byname_optional(pdev, "host");
|
|
if (irq < 0) {
|
|
if (irq == -EPROBE_DEFER)
|
|
return irq;
|
|
|
|
/* for backward compatibility */
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
}
|
|
|
|
wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
|
|
if (wakeup_irq == -EPROBE_DEFER)
|
|
return wakeup_irq;
|
|
|
|
mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
|
|
mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
|
|
/* optional property, ignore the error if it does not exist */
|
|
of_property_read_u32(node, "mediatek,u3p-dis-msk",
|
|
&mtk->u3p_dis_msk);
|
|
of_property_read_u32(node, "mediatek,u2p-dis-msk",
|
|
&mtk->u2p_dis_msk);
|
|
|
|
ret = usb_wakeup_of_property_parse(mtk, node);
|
|
if (ret) {
|
|
dev_err(dev, "failed to parse uwk property\n");
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_use_autosuspend(dev);
|
|
pm_runtime_set_autosuspend_delay(dev, 4000);
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_get_sync(dev);
|
|
|
|
ret = xhci_mtk_ldos_enable(mtk);
|
|
if (ret)
|
|
goto disable_pm;
|
|
|
|
ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
|
|
if (ret)
|
|
goto disable_ldos;
|
|
|
|
hcd = usb_create_hcd(driver, dev, dev_name(dev));
|
|
if (!hcd) {
|
|
ret = -ENOMEM;
|
|
goto disable_clk;
|
|
}
|
|
|
|
/*
|
|
* USB 2.0 roothub is stored in the platform_device.
|
|
* Swap it with mtk HCD.
|
|
*/
|
|
mtk->hcd = platform_get_drvdata(pdev);
|
|
platform_set_drvdata(pdev, mtk);
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
|
|
hcd->regs = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(hcd->regs)) {
|
|
ret = PTR_ERR(hcd->regs);
|
|
goto put_usb2_hcd;
|
|
}
|
|
hcd->rsrc_start = res->start;
|
|
hcd->rsrc_len = resource_size(res);
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
|
|
if (res) { /* ippc register is optional */
|
|
mtk->ippc_regs = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(mtk->ippc_regs)) {
|
|
ret = PTR_ERR(mtk->ippc_regs);
|
|
goto put_usb2_hcd;
|
|
}
|
|
mtk->has_ippc = true;
|
|
}
|
|
|
|
device_init_wakeup(dev, true);
|
|
|
|
xhci = hcd_to_xhci(hcd);
|
|
xhci->main_hcd = hcd;
|
|
|
|
/*
|
|
* imod_interval is the interrupt moderation value in nanoseconds.
|
|
* The increment interval is 8 times as much as that defined in
|
|
* the xHCI spec on MTK's controller.
|
|
*/
|
|
xhci->imod_interval = 5000;
|
|
device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
|
|
|
|
xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
|
|
dev_name(dev), hcd);
|
|
if (!xhci->shared_hcd) {
|
|
ret = -ENOMEM;
|
|
goto disable_device_wakeup;
|
|
}
|
|
|
|
ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
|
|
if (ret)
|
|
goto put_usb3_hcd;
|
|
|
|
if (HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
|
|
!(xhci->quirks & XHCI_BROKEN_STREAMS))
|
|
xhci->shared_hcd->can_do_streams = 1;
|
|
|
|
ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
|
|
if (ret)
|
|
goto dealloc_usb2_hcd;
|
|
|
|
if (wakeup_irq > 0) {
|
|
ret = dev_pm_set_dedicated_wake_irq(dev, wakeup_irq);
|
|
if (ret) {
|
|
dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq);
|
|
goto dealloc_usb3_hcd;
|
|
}
|
|
dev_info(dev, "wakeup irq %d\n", wakeup_irq);
|
|
}
|
|
|
|
device_enable_async_suspend(dev);
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_put_autosuspend(dev);
|
|
pm_runtime_forbid(dev);
|
|
|
|
return 0;
|
|
|
|
dealloc_usb3_hcd:
|
|
usb_remove_hcd(xhci->shared_hcd);
|
|
xhci->shared_hcd = NULL;
|
|
|
|
dealloc_usb2_hcd:
|
|
usb_remove_hcd(hcd);
|
|
|
|
put_usb3_hcd:
|
|
xhci_mtk_sch_exit(mtk);
|
|
usb_put_hcd(xhci->shared_hcd);
|
|
|
|
disable_device_wakeup:
|
|
device_init_wakeup(dev, false);
|
|
|
|
put_usb2_hcd:
|
|
usb_put_hcd(hcd);
|
|
|
|
disable_clk:
|
|
clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
|
|
|
|
disable_ldos:
|
|
xhci_mtk_ldos_disable(mtk);
|
|
|
|
disable_pm:
|
|
pm_runtime_put_noidle(dev);
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int xhci_mtk_remove(struct platform_device *pdev)
|
|
{
|
|
struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev);
|
|
struct usb_hcd *hcd = mtk->hcd;
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
struct usb_hcd *shared_hcd = xhci->shared_hcd;
|
|
struct device *dev = &pdev->dev;
|
|
|
|
pm_runtime_get_sync(dev);
|
|
xhci->xhc_state |= XHCI_STATE_REMOVING;
|
|
dev_pm_clear_wake_irq(dev);
|
|
device_init_wakeup(dev, false);
|
|
|
|
usb_remove_hcd(shared_hcd);
|
|
xhci->shared_hcd = NULL;
|
|
usb_remove_hcd(hcd);
|
|
usb_put_hcd(shared_hcd);
|
|
usb_put_hcd(hcd);
|
|
xhci_mtk_sch_exit(mtk);
|
|
clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
|
|
xhci_mtk_ldos_disable(mtk);
|
|
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_put_noidle(dev);
|
|
pm_runtime_set_suspended(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused xhci_mtk_suspend(struct device *dev)
|
|
{
|
|
struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
|
|
struct usb_hcd *hcd = mtk->hcd;
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
int ret;
|
|
|
|
xhci_dbg(xhci, "%s: stop port polling\n", __func__);
|
|
clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
|
|
del_timer_sync(&hcd->rh_timer);
|
|
clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
|
|
del_timer_sync(&xhci->shared_hcd->rh_timer);
|
|
|
|
ret = xhci_mtk_host_disable(mtk);
|
|
if (ret)
|
|
goto restart_poll_rh;
|
|
|
|
clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
|
|
usb_wakeup_set(mtk, true);
|
|
return 0;
|
|
|
|
restart_poll_rh:
|
|
xhci_dbg(xhci, "%s: restart port polling\n", __func__);
|
|
set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
|
|
usb_hcd_poll_rh_status(xhci->shared_hcd);
|
|
set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
|
|
usb_hcd_poll_rh_status(hcd);
|
|
return ret;
|
|
}
|
|
|
|
static int __maybe_unused xhci_mtk_resume(struct device *dev)
|
|
{
|
|
struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
|
|
struct usb_hcd *hcd = mtk->hcd;
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
int ret;
|
|
|
|
usb_wakeup_set(mtk, false);
|
|
ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
|
|
if (ret)
|
|
goto enable_wakeup;
|
|
|
|
ret = xhci_mtk_host_enable(mtk);
|
|
if (ret)
|
|
goto disable_clks;
|
|
|
|
xhci_dbg(xhci, "%s: restart port polling\n", __func__);
|
|
set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
|
|
usb_hcd_poll_rh_status(xhci->shared_hcd);
|
|
set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
|
|
usb_hcd_poll_rh_status(hcd);
|
|
return 0;
|
|
|
|
disable_clks:
|
|
clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
|
|
enable_wakeup:
|
|
usb_wakeup_set(mtk, true);
|
|
return ret;
|
|
}
|
|
|
|
static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev)
|
|
{
|
|
struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
|
|
struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
|
|
int ret = 0;
|
|
|
|
if (xhci->xhc_state)
|
|
return -ESHUTDOWN;
|
|
|
|
if (device_may_wakeup(dev))
|
|
ret = xhci_mtk_suspend(dev);
|
|
|
|
/* -EBUSY: let PM automatically reschedule another autosuspend */
|
|
return ret ? -EBUSY : 0;
|
|
}
|
|
|
|
static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev)
|
|
{
|
|
struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
|
|
struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
|
|
int ret = 0;
|
|
|
|
if (xhci->xhc_state)
|
|
return -ESHUTDOWN;
|
|
|
|
if (device_may_wakeup(dev))
|
|
ret = xhci_mtk_resume(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops xhci_mtk_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
|
|
SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend,
|
|
xhci_mtk_runtime_resume, NULL)
|
|
};
|
|
|
|
#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL)
|
|
|
|
static const struct of_device_id mtk_xhci_of_match[] = {
|
|
{ .compatible = "mediatek,mt8173-xhci"},
|
|
{ .compatible = "mediatek,mt8195-xhci"},
|
|
{ .compatible = "mediatek,mtk-xhci"},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
|
|
|
|
static struct platform_driver mtk_xhci_driver = {
|
|
.probe = xhci_mtk_probe,
|
|
.remove = xhci_mtk_remove,
|
|
.driver = {
|
|
.name = "xhci-mtk",
|
|
.pm = DEV_PM_OPS,
|
|
.of_match_table = mtk_xhci_of_match,
|
|
},
|
|
};
|
|
|
|
static int __init xhci_mtk_init(void)
|
|
{
|
|
xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
|
|
return platform_driver_register(&mtk_xhci_driver);
|
|
}
|
|
module_init(xhci_mtk_init);
|
|
|
|
static void __exit xhci_mtk_exit(void)
|
|
{
|
|
platform_driver_unregister(&mtk_xhci_driver);
|
|
}
|
|
module_exit(xhci_mtk_exit);
|
|
|
|
MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
|
|
MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
|
|
MODULE_LICENSE("GPL v2");
|