1196 lines
32 KiB
C
1196 lines
32 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit)
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*
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* Copyright (C) 2014 Samsung Electronics
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* Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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* Lukasz Majewski <l.majewski@samsung.com>
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*
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* Copyright (C) 2011 Samsung Electronics
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* Donggeun Kim <dg77.kim@samsung.com>
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* Amit Daniel Kachhap <amit.kachhap@linaro.org>
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/thermal/thermal_exynos.h>
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#include "../thermal_core.h"
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/* Exynos generic registers */
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#define EXYNOS_TMU_REG_TRIMINFO 0x0
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#define EXYNOS_TMU_REG_CONTROL 0x20
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#define EXYNOS_TMU_REG_STATUS 0x28
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#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
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#define EXYNOS_TMU_REG_INTEN 0x70
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#define EXYNOS_TMU_REG_INTSTAT 0x74
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#define EXYNOS_TMU_REG_INTCLEAR 0x78
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#define EXYNOS_TMU_TEMP_MASK 0xff
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#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
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#define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
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#define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
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#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
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#define EXYNOS_TMU_CORE_EN_SHIFT 0
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/* Exynos3250 specific registers */
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#define EXYNOS_TMU_TRIMINFO_CON1 0x10
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/* Exynos4210 specific registers */
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#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
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#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
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/* Exynos5250, Exynos4412, Exynos3250 specific registers */
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#define EXYNOS_TMU_TRIMINFO_CON2 0x14
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#define EXYNOS_THD_TEMP_RISE 0x50
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#define EXYNOS_THD_TEMP_FALL 0x54
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#define EXYNOS_EMUL_CON 0x80
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#define EXYNOS_TRIMINFO_RELOAD_ENABLE 1
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#define EXYNOS_TRIMINFO_25_SHIFT 0
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#define EXYNOS_TRIMINFO_85_SHIFT 8
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#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
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#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
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#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
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#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
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#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
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#define EXYNOS_EMUL_TIME 0x57F0
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#define EXYNOS_EMUL_TIME_MASK 0xffff
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#define EXYNOS_EMUL_TIME_SHIFT 16
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#define EXYNOS_EMUL_DATA_SHIFT 8
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#define EXYNOS_EMUL_DATA_MASK 0xFF
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#define EXYNOS_EMUL_ENABLE 0x1
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/* Exynos5260 specific */
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#define EXYNOS5260_TMU_REG_INTEN 0xC0
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#define EXYNOS5260_TMU_REG_INTSTAT 0xC4
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#define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
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#define EXYNOS5260_EMUL_CON 0x100
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/* Exynos4412 specific */
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#define EXYNOS4412_MUX_ADDR_VALUE 6
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#define EXYNOS4412_MUX_ADDR_SHIFT 20
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/* Exynos5433 specific registers */
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#define EXYNOS5433_THD_TEMP_RISE3_0 0x050
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#define EXYNOS5433_THD_TEMP_RISE7_4 0x054
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#define EXYNOS5433_THD_TEMP_FALL3_0 0x060
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#define EXYNOS5433_THD_TEMP_FALL7_4 0x064
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#define EXYNOS5433_TMU_REG_INTEN 0x0c0
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#define EXYNOS5433_TMU_REG_INTPEND 0x0c8
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#define EXYNOS5433_TMU_EMUL_CON 0x110
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#define EXYNOS5433_TMU_PD_DET_EN 0x130
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#define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16
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#define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23
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#define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \
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(0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT)
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#define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23)
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#define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0
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#define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1
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#define EXYNOS5433_PD_DET_EN 1
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#define EXYNOS5433_G3D_BASE 0x10070000
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/* Exynos7 specific registers */
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#define EXYNOS7_THD_TEMP_RISE7_6 0x50
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#define EXYNOS7_THD_TEMP_FALL7_6 0x60
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#define EXYNOS7_TMU_REG_INTEN 0x110
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#define EXYNOS7_TMU_REG_INTPEND 0x118
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#define EXYNOS7_TMU_REG_EMUL_CON 0x160
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#define EXYNOS7_TMU_TEMP_MASK 0x1ff
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#define EXYNOS7_PD_DET_EN_SHIFT 23
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#define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0
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#define EXYNOS7_EMUL_DATA_SHIFT 7
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#define EXYNOS7_EMUL_DATA_MASK 0x1ff
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#define EXYNOS_FIRST_POINT_TRIM 25
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#define EXYNOS_SECOND_POINT_TRIM 85
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#define EXYNOS_NOISE_CANCEL_MODE 4
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#define MCELSIUS 1000
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enum soc_type {
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SOC_ARCH_EXYNOS3250 = 1,
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SOC_ARCH_EXYNOS4210,
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SOC_ARCH_EXYNOS4412,
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SOC_ARCH_EXYNOS5250,
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SOC_ARCH_EXYNOS5260,
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SOC_ARCH_EXYNOS5420,
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SOC_ARCH_EXYNOS5420_TRIMINFO,
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SOC_ARCH_EXYNOS5433,
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SOC_ARCH_EXYNOS7,
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};
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/**
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* struct exynos_tmu_data : A structure to hold the private data of the TMU
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* driver
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* @id: identifier of the one instance of the TMU controller.
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* @base: base address of the single instance of the TMU controller.
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* @base_second: base address of the common registers of the TMU controller.
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* @irq: irq number of the TMU controller.
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* @soc: id of the SOC type.
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* @irq_work: pointer to the irq work structure.
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* @lock: lock to implement synchronization.
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* @clk: pointer to the clock structure.
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* @clk_sec: pointer to the clock structure for accessing the base_second.
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* @sclk: pointer to the clock structure for accessing the tmu special clk.
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* @cal_type: calibration type for temperature
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* @efuse_value: SoC defined fuse value
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* @min_efuse_value: minimum valid trimming data
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* @max_efuse_value: maximum valid trimming data
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* @temp_error1: fused value of the first point trim.
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* @temp_error2: fused value of the second point trim.
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* @gain: gain of amplifier in the positive-TC generator block
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* 0 < gain <= 15
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* @reference_voltage: reference voltage of amplifier
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* in the positive-TC generator block
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* 0 < reference_voltage <= 31
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* @regulator: pointer to the TMU regulator structure.
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* @reg_conf: pointer to structure to register with core thermal.
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* @tzd: pointer to thermal_zone_device structure
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* @ntrip: number of supported trip points.
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* @enabled: current status of TMU device
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* @tmu_set_trip_temp: SoC specific method to set trip (rising threshold)
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* @tmu_set_trip_hyst: SoC specific to set hysteresis (falling threshold)
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* @tmu_initialize: SoC specific TMU initialization method
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* @tmu_control: SoC specific TMU control method
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* @tmu_read: SoC specific TMU temperature read method
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* @tmu_set_emulation: SoC specific TMU emulation setting method
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* @tmu_clear_irqs: SoC specific TMU interrupts clearing method
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*/
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struct exynos_tmu_data {
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int id;
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void __iomem *base;
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void __iomem *base_second;
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int irq;
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enum soc_type soc;
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struct work_struct irq_work;
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struct mutex lock;
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struct clk *clk, *clk_sec, *sclk;
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u32 cal_type;
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u32 efuse_value;
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u32 min_efuse_value;
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u32 max_efuse_value;
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u16 temp_error1, temp_error2;
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u8 gain;
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u8 reference_voltage;
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struct regulator *regulator;
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struct thermal_zone_device *tzd;
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unsigned int ntrip;
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bool enabled;
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void (*tmu_set_trip_temp)(struct exynos_tmu_data *data, int trip,
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u8 temp);
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void (*tmu_set_trip_hyst)(struct exynos_tmu_data *data, int trip,
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u8 temp, u8 hyst);
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void (*tmu_initialize)(struct platform_device *pdev);
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void (*tmu_control)(struct platform_device *pdev, bool on);
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int (*tmu_read)(struct exynos_tmu_data *data);
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void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp);
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void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
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};
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/*
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* TMU treats temperature as a mapped temperature code.
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* The temperature is converted differently depending on the calibration type.
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*/
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static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
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{
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if (data->cal_type == TYPE_ONE_POINT_TRIMMING)
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return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM;
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return (temp - EXYNOS_FIRST_POINT_TRIM) *
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(data->temp_error2 - data->temp_error1) /
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(EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) +
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data->temp_error1;
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}
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/*
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* Calculate a temperature value from a temperature code.
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* The unit of the temperature is degree Celsius.
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*/
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static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
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{
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if (data->cal_type == TYPE_ONE_POINT_TRIMMING)
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return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM;
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return (temp_code - data->temp_error1) *
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(EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) /
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(data->temp_error2 - data->temp_error1) +
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EXYNOS_FIRST_POINT_TRIM;
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}
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static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
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{
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u16 tmu_temp_mask =
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(data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK
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: EXYNOS_TMU_TEMP_MASK;
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data->temp_error1 = trim_info & tmu_temp_mask;
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data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
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EXYNOS_TMU_TEMP_MASK);
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if (!data->temp_error1 ||
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(data->min_efuse_value > data->temp_error1) ||
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(data->temp_error1 > data->max_efuse_value))
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data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
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if (!data->temp_error2)
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data->temp_error2 =
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(data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
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EXYNOS_TMU_TEMP_MASK;
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}
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static int exynos_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct thermal_zone_device *tzd = data->tzd;
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const struct thermal_trip * const trips =
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of_thermal_get_trip_points(tzd);
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unsigned int status;
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int ret = 0, temp, hyst;
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if (!trips) {
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dev_err(&pdev->dev,
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"Cannot get trip points from device tree!\n");
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return -ENODEV;
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}
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if (data->soc != SOC_ARCH_EXYNOS5433) /* FIXME */
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ret = tzd->ops->get_crit_temp(tzd, &temp);
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if (ret) {
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dev_err(&pdev->dev,
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"No CRITICAL trip point defined in device tree!\n");
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goto out;
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}
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if (of_thermal_get_ntrips(tzd) > data->ntrip) {
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dev_info(&pdev->dev,
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"More trip points than supported by this TMU.\n");
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dev_info(&pdev->dev,
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"%d trip points should be configured in polling mode.\n",
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(of_thermal_get_ntrips(tzd) - data->ntrip));
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}
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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if (!IS_ERR(data->clk_sec))
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clk_enable(data->clk_sec);
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status = readb(data->base + EXYNOS_TMU_REG_STATUS);
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if (!status) {
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ret = -EBUSY;
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} else {
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int i, ntrips =
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min_t(int, of_thermal_get_ntrips(tzd), data->ntrip);
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data->tmu_initialize(pdev);
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/* Write temperature code for rising and falling threshold */
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for (i = 0; i < ntrips; i++) {
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/* Write temperature code for rising threshold */
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ret = tzd->ops->get_trip_temp(tzd, i, &temp);
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if (ret)
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goto err;
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temp /= MCELSIUS;
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data->tmu_set_trip_temp(data, i, temp);
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/* Write temperature code for falling threshold */
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ret = tzd->ops->get_trip_hyst(tzd, i, &hyst);
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if (ret)
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goto err;
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hyst /= MCELSIUS;
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data->tmu_set_trip_hyst(data, i, temp, hyst);
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}
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data->tmu_clear_irqs(data);
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}
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err:
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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if (!IS_ERR(data->clk_sec))
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clk_disable(data->clk_sec);
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out:
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return ret;
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}
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static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
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{
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if (data->soc == SOC_ARCH_EXYNOS4412 ||
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data->soc == SOC_ARCH_EXYNOS3250)
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con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT);
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con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
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con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
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con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
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con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
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con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
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con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT);
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return con;
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}
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static void exynos_tmu_control(struct platform_device *pdev, bool on)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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data->tmu_control(pdev, on);
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data->enabled = on;
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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}
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static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data,
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int trip, u8 temp)
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{
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const struct thermal_trip * const trips =
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of_thermal_get_trip_points(data->tzd);
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u8 ref, th_code;
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ref = trips[0].temperature / MCELSIUS;
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if (trip == 0) {
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th_code = temp_to_code(data, ref);
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writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
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}
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temp -= ref;
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writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip * 4);
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}
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/* failing thresholds are not supported on Exynos4210 */
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static void exynos4210_tmu_set_trip_hyst(struct exynos_tmu_data *data,
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int trip, u8 temp, u8 hyst)
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{
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}
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static void exynos4210_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
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}
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static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data,
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int trip, u8 temp)
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{
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u32 th, con;
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th = readl(data->base + EXYNOS_THD_TEMP_RISE);
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th &= ~(0xff << 8 * trip);
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th |= temp_to_code(data, temp) << 8 * trip;
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writel(th, data->base + EXYNOS_THD_TEMP_RISE);
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if (trip == 3) {
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con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
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con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
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writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
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}
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}
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static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data,
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int trip, u8 temp, u8 hyst)
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{
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u32 th;
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th = readl(data->base + EXYNOS_THD_TEMP_FALL);
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th &= ~(0xff << 8 * trip);
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if (hyst)
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th |= temp_to_code(data, temp - hyst) << 8 * trip;
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writel(th, data->base + EXYNOS_THD_TEMP_FALL);
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}
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static void exynos4412_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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unsigned int trim_info, ctrl;
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if (data->soc == SOC_ARCH_EXYNOS3250 ||
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data->soc == SOC_ARCH_EXYNOS4412 ||
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data->soc == SOC_ARCH_EXYNOS5250) {
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if (data->soc == SOC_ARCH_EXYNOS3250) {
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ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
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ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
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writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
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}
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ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
|
|
ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
|
|
writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
|
|
}
|
|
|
|
/* On exynos5420 the triminfo register is in the shared space */
|
|
if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
|
|
trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
|
|
else
|
|
trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
|
|
|
|
sanitize_temp_error(data, trim_info);
|
|
}
|
|
|
|
static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data,
|
|
int trip, u8 temp)
|
|
{
|
|
unsigned int reg_off, j;
|
|
u32 th;
|
|
|
|
if (trip > 3) {
|
|
reg_off = EXYNOS5433_THD_TEMP_RISE7_4;
|
|
j = trip - 4;
|
|
} else {
|
|
reg_off = EXYNOS5433_THD_TEMP_RISE3_0;
|
|
j = trip;
|
|
}
|
|
|
|
th = readl(data->base + reg_off);
|
|
th &= ~(0xff << j * 8);
|
|
th |= (temp_to_code(data, temp) << j * 8);
|
|
writel(th, data->base + reg_off);
|
|
}
|
|
|
|
static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data,
|
|
int trip, u8 temp, u8 hyst)
|
|
{
|
|
unsigned int reg_off, j;
|
|
u32 th;
|
|
|
|
if (trip > 3) {
|
|
reg_off = EXYNOS5433_THD_TEMP_FALL7_4;
|
|
j = trip - 4;
|
|
} else {
|
|
reg_off = EXYNOS5433_THD_TEMP_FALL3_0;
|
|
j = trip;
|
|
}
|
|
|
|
th = readl(data->base + reg_off);
|
|
th &= ~(0xff << j * 8);
|
|
th |= (temp_to_code(data, temp - hyst) << j * 8);
|
|
writel(th, data->base + reg_off);
|
|
}
|
|
|
|
static void exynos5433_tmu_initialize(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
unsigned int trim_info;
|
|
int sensor_id, cal_type;
|
|
|
|
trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
|
|
sanitize_temp_error(data, trim_info);
|
|
|
|
/* Read the temperature sensor id */
|
|
sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK)
|
|
>> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT;
|
|
dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id);
|
|
|
|
/* Read the calibration mode */
|
|
writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO);
|
|
cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK)
|
|
>> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT;
|
|
|
|
switch (cal_type) {
|
|
case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING:
|
|
data->cal_type = TYPE_TWO_POINT_TRIMMING;
|
|
break;
|
|
case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING:
|
|
default:
|
|
data->cal_type = TYPE_ONE_POINT_TRIMMING;
|
|
break;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Calibration type is %d-point calibration\n",
|
|
cal_type ? 2 : 1);
|
|
}
|
|
|
|
static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data,
|
|
int trip, u8 temp)
|
|
{
|
|
unsigned int reg_off, bit_off;
|
|
u32 th;
|
|
|
|
reg_off = ((7 - trip) / 2) * 4;
|
|
bit_off = ((8 - trip) % 2);
|
|
|
|
th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
|
|
th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
|
|
th |= temp_to_code(data, temp) << (16 * bit_off);
|
|
writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
|
|
}
|
|
|
|
static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data,
|
|
int trip, u8 temp, u8 hyst)
|
|
{
|
|
unsigned int reg_off, bit_off;
|
|
u32 th;
|
|
|
|
reg_off = ((7 - trip) / 2) * 4;
|
|
bit_off = ((8 - trip) % 2);
|
|
|
|
th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
|
|
th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
|
|
th |= temp_to_code(data, temp - hyst) << (16 * bit_off);
|
|
writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
|
|
}
|
|
|
|
static void exynos7_tmu_initialize(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
unsigned int trim_info;
|
|
|
|
trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
|
|
sanitize_temp_error(data, trim_info);
|
|
}
|
|
|
|
static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct thermal_zone_device *tz = data->tzd;
|
|
unsigned int con, interrupt_en = 0, i;
|
|
|
|
con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
|
|
|
|
if (on) {
|
|
for (i = 0; i < data->ntrip; i++) {
|
|
if (!of_thermal_is_trip_valid(tz, i))
|
|
continue;
|
|
|
|
interrupt_en |=
|
|
(1 << (EXYNOS_TMU_INTEN_RISE0_SHIFT + i * 4));
|
|
}
|
|
|
|
if (data->soc != SOC_ARCH_EXYNOS4210)
|
|
interrupt_en |=
|
|
interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
|
|
|
|
con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
} else {
|
|
con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
}
|
|
|
|
writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
|
|
writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
|
|
}
|
|
|
|
static void exynos5433_tmu_control(struct platform_device *pdev, bool on)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct thermal_zone_device *tz = data->tzd;
|
|
unsigned int con, interrupt_en = 0, pd_det_en, i;
|
|
|
|
con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
|
|
|
|
if (on) {
|
|
for (i = 0; i < data->ntrip; i++) {
|
|
if (!of_thermal_is_trip_valid(tz, i))
|
|
continue;
|
|
|
|
interrupt_en |=
|
|
(1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i));
|
|
}
|
|
|
|
interrupt_en |=
|
|
interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
|
|
|
|
con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
} else
|
|
con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
|
|
pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0;
|
|
|
|
writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN);
|
|
writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN);
|
|
writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
|
|
}
|
|
|
|
static void exynos7_tmu_control(struct platform_device *pdev, bool on)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct thermal_zone_device *tz = data->tzd;
|
|
unsigned int con, interrupt_en = 0, i;
|
|
|
|
con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
|
|
|
|
if (on) {
|
|
for (i = 0; i < data->ntrip; i++) {
|
|
if (!of_thermal_is_trip_valid(tz, i))
|
|
continue;
|
|
|
|
interrupt_en |=
|
|
(1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i));
|
|
}
|
|
|
|
interrupt_en |=
|
|
interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
|
|
|
|
con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
con |= (1 << EXYNOS7_PD_DET_EN_SHIFT);
|
|
} else {
|
|
con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
|
|
con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT);
|
|
}
|
|
|
|
writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN);
|
|
writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
|
|
}
|
|
|
|
static int exynos_get_temp(void *p, int *temp)
|
|
{
|
|
struct exynos_tmu_data *data = p;
|
|
int value, ret = 0;
|
|
|
|
if (!data || !data->tmu_read)
|
|
return -EINVAL;
|
|
else if (!data->enabled)
|
|
/*
|
|
* Called too early, probably
|
|
* from thermal_zone_of_sensor_register().
|
|
*/
|
|
return -EAGAIN;
|
|
|
|
mutex_lock(&data->lock);
|
|
clk_enable(data->clk);
|
|
|
|
value = data->tmu_read(data);
|
|
if (value < 0)
|
|
ret = value;
|
|
else
|
|
*temp = code_to_temp(data, value) * MCELSIUS;
|
|
|
|
clk_disable(data->clk);
|
|
mutex_unlock(&data->lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_THERMAL_EMULATION
|
|
static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
|
|
int temp)
|
|
{
|
|
if (temp) {
|
|
temp /= MCELSIUS;
|
|
|
|
val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
|
|
val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
|
|
if (data->soc == SOC_ARCH_EXYNOS7) {
|
|
val &= ~(EXYNOS7_EMUL_DATA_MASK <<
|
|
EXYNOS7_EMUL_DATA_SHIFT);
|
|
val |= (temp_to_code(data, temp) <<
|
|
EXYNOS7_EMUL_DATA_SHIFT) |
|
|
EXYNOS_EMUL_ENABLE;
|
|
} else {
|
|
val &= ~(EXYNOS_EMUL_DATA_MASK <<
|
|
EXYNOS_EMUL_DATA_SHIFT);
|
|
val |= (temp_to_code(data, temp) <<
|
|
EXYNOS_EMUL_DATA_SHIFT) |
|
|
EXYNOS_EMUL_ENABLE;
|
|
}
|
|
} else {
|
|
val &= ~EXYNOS_EMUL_ENABLE;
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
|
|
int temp)
|
|
{
|
|
unsigned int val;
|
|
u32 emul_con;
|
|
|
|
if (data->soc == SOC_ARCH_EXYNOS5260)
|
|
emul_con = EXYNOS5260_EMUL_CON;
|
|
else if (data->soc == SOC_ARCH_EXYNOS5433)
|
|
emul_con = EXYNOS5433_TMU_EMUL_CON;
|
|
else if (data->soc == SOC_ARCH_EXYNOS7)
|
|
emul_con = EXYNOS7_TMU_REG_EMUL_CON;
|
|
else
|
|
emul_con = EXYNOS_EMUL_CON;
|
|
|
|
val = readl(data->base + emul_con);
|
|
val = get_emul_con_reg(data, val, temp);
|
|
writel(val, data->base + emul_con);
|
|
}
|
|
|
|
static int exynos_tmu_set_emulation(void *drv_data, int temp)
|
|
{
|
|
struct exynos_tmu_data *data = drv_data;
|
|
int ret = -EINVAL;
|
|
|
|
if (data->soc == SOC_ARCH_EXYNOS4210)
|
|
goto out;
|
|
|
|
if (temp && temp < MCELSIUS)
|
|
goto out;
|
|
|
|
mutex_lock(&data->lock);
|
|
clk_enable(data->clk);
|
|
data->tmu_set_emulation(data, temp);
|
|
clk_disable(data->clk);
|
|
mutex_unlock(&data->lock);
|
|
return 0;
|
|
out:
|
|
return ret;
|
|
}
|
|
#else
|
|
#define exynos4412_tmu_set_emulation NULL
|
|
static int exynos_tmu_set_emulation(void *drv_data, int temp)
|
|
{ return -EINVAL; }
|
|
#endif /* CONFIG_THERMAL_EMULATION */
|
|
|
|
static int exynos4210_tmu_read(struct exynos_tmu_data *data)
|
|
{
|
|
int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
|
|
|
|
/* "temp_code" should range between 75 and 175 */
|
|
return (ret < 75 || ret > 175) ? -ENODATA : ret;
|
|
}
|
|
|
|
static int exynos4412_tmu_read(struct exynos_tmu_data *data)
|
|
{
|
|
return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
|
|
}
|
|
|
|
static int exynos7_tmu_read(struct exynos_tmu_data *data)
|
|
{
|
|
return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &
|
|
EXYNOS7_TMU_TEMP_MASK;
|
|
}
|
|
|
|
static void exynos_tmu_work(struct work_struct *work)
|
|
{
|
|
struct exynos_tmu_data *data = container_of(work,
|
|
struct exynos_tmu_data, irq_work);
|
|
|
|
thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED);
|
|
|
|
mutex_lock(&data->lock);
|
|
clk_enable(data->clk);
|
|
|
|
/* TODO: take action based on particular interrupt */
|
|
data->tmu_clear_irqs(data);
|
|
|
|
clk_disable(data->clk);
|
|
mutex_unlock(&data->lock);
|
|
enable_irq(data->irq);
|
|
}
|
|
|
|
static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
|
|
{
|
|
unsigned int val_irq;
|
|
u32 tmu_intstat, tmu_intclear;
|
|
|
|
if (data->soc == SOC_ARCH_EXYNOS5260) {
|
|
tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
|
|
tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
|
|
} else if (data->soc == SOC_ARCH_EXYNOS7) {
|
|
tmu_intstat = EXYNOS7_TMU_REG_INTPEND;
|
|
tmu_intclear = EXYNOS7_TMU_REG_INTPEND;
|
|
} else if (data->soc == SOC_ARCH_EXYNOS5433) {
|
|
tmu_intstat = EXYNOS5433_TMU_REG_INTPEND;
|
|
tmu_intclear = EXYNOS5433_TMU_REG_INTPEND;
|
|
} else {
|
|
tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
|
|
tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
|
|
}
|
|
|
|
val_irq = readl(data->base + tmu_intstat);
|
|
/*
|
|
* Clear the interrupts. Please note that the documentation for
|
|
* Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
|
|
* states that INTCLEAR register has a different placing of bits
|
|
* responsible for FALL IRQs than INTSTAT register. Exynos5420
|
|
* and Exynos5440 documentation is correct (Exynos4210 doesn't
|
|
* support FALL IRQs at all).
|
|
*/
|
|
writel(val_irq, data->base + tmu_intclear);
|
|
}
|
|
|
|
static irqreturn_t exynos_tmu_irq(int irq, void *id)
|
|
{
|
|
struct exynos_tmu_data *data = id;
|
|
|
|
disable_irq_nosync(irq);
|
|
schedule_work(&data->irq_work);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const struct of_device_id exynos_tmu_match[] = {
|
|
{
|
|
.compatible = "samsung,exynos3250-tmu",
|
|
.data = (const void *)SOC_ARCH_EXYNOS3250,
|
|
}, {
|
|
.compatible = "samsung,exynos4210-tmu",
|
|
.data = (const void *)SOC_ARCH_EXYNOS4210,
|
|
}, {
|
|
.compatible = "samsung,exynos4412-tmu",
|
|
.data = (const void *)SOC_ARCH_EXYNOS4412,
|
|
}, {
|
|
.compatible = "samsung,exynos5250-tmu",
|
|
.data = (const void *)SOC_ARCH_EXYNOS5250,
|
|
}, {
|
|
.compatible = "samsung,exynos5260-tmu",
|
|
.data = (const void *)SOC_ARCH_EXYNOS5260,
|
|
}, {
|
|
.compatible = "samsung,exynos5420-tmu",
|
|
.data = (const void *)SOC_ARCH_EXYNOS5420,
|
|
}, {
|
|
.compatible = "samsung,exynos5420-tmu-ext-triminfo",
|
|
.data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO,
|
|
}, {
|
|
.compatible = "samsung,exynos5433-tmu",
|
|
.data = (const void *)SOC_ARCH_EXYNOS5433,
|
|
}, {
|
|
.compatible = "samsung,exynos7-tmu",
|
|
.data = (const void *)SOC_ARCH_EXYNOS7,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, exynos_tmu_match);
|
|
|
|
static int exynos_map_dt_data(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct resource res;
|
|
|
|
if (!data || !pdev->dev.of_node)
|
|
return -ENODEV;
|
|
|
|
data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
|
|
if (data->id < 0)
|
|
data->id = 0;
|
|
|
|
data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
|
|
if (data->irq <= 0) {
|
|
dev_err(&pdev->dev, "failed to get IRQ\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
|
|
dev_err(&pdev->dev, "failed to get Resource 0\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
|
|
if (!data->base) {
|
|
dev_err(&pdev->dev, "Failed to ioremap memory\n");
|
|
return -EADDRNOTAVAIL;
|
|
}
|
|
|
|
data->soc = (enum soc_type)of_device_get_match_data(&pdev->dev);
|
|
|
|
switch (data->soc) {
|
|
case SOC_ARCH_EXYNOS4210:
|
|
data->tmu_set_trip_temp = exynos4210_tmu_set_trip_temp;
|
|
data->tmu_set_trip_hyst = exynos4210_tmu_set_trip_hyst;
|
|
data->tmu_initialize = exynos4210_tmu_initialize;
|
|
data->tmu_control = exynos4210_tmu_control;
|
|
data->tmu_read = exynos4210_tmu_read;
|
|
data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
|
|
data->ntrip = 4;
|
|
data->gain = 15;
|
|
data->reference_voltage = 7;
|
|
data->efuse_value = 55;
|
|
data->min_efuse_value = 40;
|
|
data->max_efuse_value = 100;
|
|
break;
|
|
case SOC_ARCH_EXYNOS3250:
|
|
case SOC_ARCH_EXYNOS4412:
|
|
case SOC_ARCH_EXYNOS5250:
|
|
case SOC_ARCH_EXYNOS5260:
|
|
case SOC_ARCH_EXYNOS5420:
|
|
case SOC_ARCH_EXYNOS5420_TRIMINFO:
|
|
data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp;
|
|
data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst;
|
|
data->tmu_initialize = exynos4412_tmu_initialize;
|
|
data->tmu_control = exynos4210_tmu_control;
|
|
data->tmu_read = exynos4412_tmu_read;
|
|
data->tmu_set_emulation = exynos4412_tmu_set_emulation;
|
|
data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
|
|
data->ntrip = 4;
|
|
data->gain = 8;
|
|
data->reference_voltage = 16;
|
|
data->efuse_value = 55;
|
|
if (data->soc != SOC_ARCH_EXYNOS5420 &&
|
|
data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
|
|
data->min_efuse_value = 40;
|
|
else
|
|
data->min_efuse_value = 0;
|
|
data->max_efuse_value = 100;
|
|
break;
|
|
case SOC_ARCH_EXYNOS5433:
|
|
data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp;
|
|
data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst;
|
|
data->tmu_initialize = exynos5433_tmu_initialize;
|
|
data->tmu_control = exynos5433_tmu_control;
|
|
data->tmu_read = exynos4412_tmu_read;
|
|
data->tmu_set_emulation = exynos4412_tmu_set_emulation;
|
|
data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
|
|
data->ntrip = 8;
|
|
data->gain = 8;
|
|
if (res.start == EXYNOS5433_G3D_BASE)
|
|
data->reference_voltage = 23;
|
|
else
|
|
data->reference_voltage = 16;
|
|
data->efuse_value = 75;
|
|
data->min_efuse_value = 40;
|
|
data->max_efuse_value = 150;
|
|
break;
|
|
case SOC_ARCH_EXYNOS7:
|
|
data->tmu_set_trip_temp = exynos7_tmu_set_trip_temp;
|
|
data->tmu_set_trip_hyst = exynos7_tmu_set_trip_hyst;
|
|
data->tmu_initialize = exynos7_tmu_initialize;
|
|
data->tmu_control = exynos7_tmu_control;
|
|
data->tmu_read = exynos7_tmu_read;
|
|
data->tmu_set_emulation = exynos4412_tmu_set_emulation;
|
|
data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
|
|
data->ntrip = 8;
|
|
data->gain = 9;
|
|
data->reference_voltage = 17;
|
|
data->efuse_value = 75;
|
|
data->min_efuse_value = 15;
|
|
data->max_efuse_value = 100;
|
|
break;
|
|
default:
|
|
dev_err(&pdev->dev, "Platform not supported\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
data->cal_type = TYPE_ONE_POINT_TRIMMING;
|
|
|
|
/*
|
|
* Check if the TMU shares some registers and then try to map the
|
|
* memory of common registers.
|
|
*/
|
|
if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
|
|
return 0;
|
|
|
|
if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
|
|
dev_err(&pdev->dev, "failed to get Resource 1\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
data->base_second = devm_ioremap(&pdev->dev, res.start,
|
|
resource_size(&res));
|
|
if (!data->base_second) {
|
|
dev_err(&pdev->dev, "Failed to ioremap memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct thermal_zone_of_device_ops exynos_sensor_ops = {
|
|
.get_temp = exynos_get_temp,
|
|
.set_emul_temp = exynos_tmu_set_emulation,
|
|
};
|
|
|
|
static int exynos_tmu_probe(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data;
|
|
int ret;
|
|
|
|
data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
|
|
GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
mutex_init(&data->lock);
|
|
|
|
/*
|
|
* Try enabling the regulator if found
|
|
* TODO: Add regulator as an SOC feature, so that regulator enable
|
|
* is a compulsory call.
|
|
*/
|
|
data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu");
|
|
if (!IS_ERR(data->regulator)) {
|
|
ret = regulator_enable(data->regulator);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to enable vtmu\n");
|
|
return ret;
|
|
}
|
|
} else {
|
|
if (PTR_ERR(data->regulator) == -EPROBE_DEFER)
|
|
return -EPROBE_DEFER;
|
|
dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
|
|
}
|
|
|
|
ret = exynos_map_dt_data(pdev);
|
|
if (ret)
|
|
goto err_sensor;
|
|
|
|
INIT_WORK(&data->irq_work, exynos_tmu_work);
|
|
|
|
data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
|
|
if (IS_ERR(data->clk)) {
|
|
dev_err(&pdev->dev, "Failed to get clock\n");
|
|
ret = PTR_ERR(data->clk);
|
|
goto err_sensor;
|
|
}
|
|
|
|
data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
|
|
if (IS_ERR(data->clk_sec)) {
|
|
if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
|
|
dev_err(&pdev->dev, "Failed to get triminfo clock\n");
|
|
ret = PTR_ERR(data->clk_sec);
|
|
goto err_sensor;
|
|
}
|
|
} else {
|
|
ret = clk_prepare(data->clk_sec);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to get clock\n");
|
|
goto err_sensor;
|
|
}
|
|
}
|
|
|
|
ret = clk_prepare(data->clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to get clock\n");
|
|
goto err_clk_sec;
|
|
}
|
|
|
|
switch (data->soc) {
|
|
case SOC_ARCH_EXYNOS5433:
|
|
case SOC_ARCH_EXYNOS7:
|
|
data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk");
|
|
if (IS_ERR(data->sclk)) {
|
|
dev_err(&pdev->dev, "Failed to get sclk\n");
|
|
ret = PTR_ERR(data->sclk);
|
|
goto err_clk;
|
|
} else {
|
|
ret = clk_prepare_enable(data->sclk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to enable sclk\n");
|
|
goto err_clk;
|
|
}
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* data->tzd must be registered before calling exynos_tmu_initialize(),
|
|
* requesting irq and calling exynos_tmu_control().
|
|
*/
|
|
data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data,
|
|
&exynos_sensor_ops);
|
|
if (IS_ERR(data->tzd)) {
|
|
ret = PTR_ERR(data->tzd);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(&pdev->dev, "Failed to register sensor: %d\n",
|
|
ret);
|
|
goto err_sclk;
|
|
}
|
|
|
|
ret = exynos_tmu_initialize(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to initialize TMU\n");
|
|
goto err_thermal;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
|
|
IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
|
|
goto err_thermal;
|
|
}
|
|
|
|
exynos_tmu_control(pdev, true);
|
|
return 0;
|
|
|
|
err_thermal:
|
|
thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd);
|
|
err_sclk:
|
|
clk_disable_unprepare(data->sclk);
|
|
err_clk:
|
|
clk_unprepare(data->clk);
|
|
err_clk_sec:
|
|
if (!IS_ERR(data->clk_sec))
|
|
clk_unprepare(data->clk_sec);
|
|
err_sensor:
|
|
if (!IS_ERR(data->regulator))
|
|
regulator_disable(data->regulator);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int exynos_tmu_remove(struct platform_device *pdev)
|
|
{
|
|
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
|
|
struct thermal_zone_device *tzd = data->tzd;
|
|
|
|
thermal_zone_of_sensor_unregister(&pdev->dev, tzd);
|
|
exynos_tmu_control(pdev, false);
|
|
|
|
clk_disable_unprepare(data->sclk);
|
|
clk_unprepare(data->clk);
|
|
if (!IS_ERR(data->clk_sec))
|
|
clk_unprepare(data->clk_sec);
|
|
|
|
if (!IS_ERR(data->regulator))
|
|
regulator_disable(data->regulator);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int exynos_tmu_suspend(struct device *dev)
|
|
{
|
|
exynos_tmu_control(to_platform_device(dev), false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int exynos_tmu_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
exynos_tmu_initialize(pdev);
|
|
exynos_tmu_control(pdev, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
|
|
exynos_tmu_suspend, exynos_tmu_resume);
|
|
#define EXYNOS_TMU_PM (&exynos_tmu_pm)
|
|
#else
|
|
#define EXYNOS_TMU_PM NULL
|
|
#endif
|
|
|
|
static struct platform_driver exynos_tmu_driver = {
|
|
.driver = {
|
|
.name = "exynos-tmu",
|
|
.pm = EXYNOS_TMU_PM,
|
|
.of_match_table = exynos_tmu_match,
|
|
},
|
|
.probe = exynos_tmu_probe,
|
|
.remove = exynos_tmu_remove,
|
|
};
|
|
|
|
module_platform_driver(exynos_tmu_driver);
|
|
|
|
MODULE_DESCRIPTION("Exynos TMU Driver");
|
|
MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:exynos-tmu");
|