620 lines
15 KiB
C
620 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* STMicroelectronics STM32 USB PHY Controller driver
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*
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* Copyright (C) 2018 STMicroelectronics
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* Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/reset.h>
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#include <linux/units.h>
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#define STM32_USBPHYC_PLL 0x0
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#define STM32_USBPHYC_MISC 0x8
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#define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
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#define STM32_USBPHYC_VERSION 0x3F4
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/* STM32_USBPHYC_PLL bit fields */
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#define PLLNDIV GENMASK(6, 0)
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#define PLLFRACIN GENMASK(25, 10)
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#define PLLEN BIT(26)
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#define PLLSTRB BIT(27)
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#define PLLSTRBYP BIT(28)
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#define PLLFRACCTL BIT(29)
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#define PLLDITHEN0 BIT(30)
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#define PLLDITHEN1 BIT(31)
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/* STM32_USBPHYC_MISC bit fields */
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#define SWITHOST BIT(0)
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/* STM32_USBPHYC_MONITOR bit fields */
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#define STM32_USBPHYC_MON_OUT GENMASK(3, 0)
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#define STM32_USBPHYC_MON_SEL GENMASK(8, 4)
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#define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
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#define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
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/* STM32_USBPHYC_VERSION bit fields */
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#define MINREV GENMASK(3, 0)
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#define MAJREV GENMASK(7, 4)
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#define PLL_FVCO_MHZ 2880
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#define PLL_INFF_MIN_RATE_HZ 19200000
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#define PLL_INFF_MAX_RATE_HZ 38400000
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struct pll_params {
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u8 ndiv;
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u16 frac;
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};
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struct stm32_usbphyc_phy {
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struct phy *phy;
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struct stm32_usbphyc *usbphyc;
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struct regulator *vbus;
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u32 index;
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bool active;
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};
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struct stm32_usbphyc {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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struct reset_control *rst;
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struct stm32_usbphyc_phy **phys;
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int nphys;
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struct regulator *vdda1v1;
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struct regulator *vdda1v8;
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atomic_t n_pll_cons;
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struct clk_hw clk48_hw;
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int switch_setup;
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};
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static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
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{
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writel_relaxed(readl_relaxed(reg) | bits, reg);
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}
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static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
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{
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writel_relaxed(readl_relaxed(reg) & ~bits, reg);
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}
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static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
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{
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int ret;
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ret = regulator_enable(usbphyc->vdda1v1);
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if (ret)
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return ret;
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ret = regulator_enable(usbphyc->vdda1v8);
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if (ret)
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goto vdda1v1_disable;
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return 0;
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vdda1v1_disable:
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regulator_disable(usbphyc->vdda1v1);
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return ret;
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}
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static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
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{
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int ret;
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ret = regulator_disable(usbphyc->vdda1v8);
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if (ret)
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return ret;
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ret = regulator_disable(usbphyc->vdda1v1);
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if (ret)
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return ret;
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return 0;
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}
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static void stm32_usbphyc_get_pll_params(u32 clk_rate,
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struct pll_params *pll_params)
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{
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unsigned long long fvco, ndiv, frac;
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/* _
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* | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
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* | FVCO = 2880MHz
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* <
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* | NDIV = integer part of input bits to set the LDF
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* |_FRACT = fractional part of input bits to set the LDF
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* => PLLNDIV = integer part of (FVCO / (INFF*2))
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* => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
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* <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
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*/
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fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
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ndiv = fvco;
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do_div(ndiv, (clk_rate * 2));
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pll_params->ndiv = (u8)ndiv;
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frac = fvco * (1 << 16);
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do_div(frac, (clk_rate * 2));
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frac = frac - (ndiv * (1 << 16));
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pll_params->frac = (u16)frac;
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}
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static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
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{
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struct pll_params pll_params;
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u32 clk_rate = clk_get_rate(usbphyc->clk);
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u32 ndiv, frac;
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u32 usbphyc_pll;
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if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
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(clk_rate > PLL_INFF_MAX_RATE_HZ)) {
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dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
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clk_rate);
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return -EINVAL;
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}
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stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
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ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
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frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
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usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
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if (pll_params.frac)
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usbphyc_pll |= PLLFRACCTL | frac;
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writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
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dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
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clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
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FIELD_GET(PLLFRACIN, usbphyc_pll));
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return 0;
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}
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static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
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{
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void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
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u32 pllen;
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stm32_usbphyc_clr_bits(pll_reg, PLLEN);
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/* Wait for minimum width of powerdown pulse (ENABLE = Low) */
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if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
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dev_err(usbphyc->dev, "PLL not reset\n");
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return stm32_usbphyc_regulators_disable(usbphyc);
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}
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static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
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{
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/* Check if a phy port is still active or clk48 in use */
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if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
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return 0;
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return __stm32_usbphyc_pll_disable(usbphyc);
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}
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static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
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{
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void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
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bool pllen = readl_relaxed(pll_reg) & PLLEN;
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int ret;
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/*
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* Check if a phy port or clk48 prepare has configured the pll
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* and ensure the PLL is enabled
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*/
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if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
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return 0;
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if (pllen) {
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/*
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* PLL shouldn't be enabled without known consumer,
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* disable it and reinit n_pll_cons
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*/
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dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
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ret = __stm32_usbphyc_pll_disable(usbphyc);
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if (ret)
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return ret;
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}
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ret = stm32_usbphyc_regulators_enable(usbphyc);
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if (ret)
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goto dec_n_pll_cons;
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ret = stm32_usbphyc_pll_init(usbphyc);
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if (ret)
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goto reg_disable;
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stm32_usbphyc_set_bits(pll_reg, PLLEN);
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return 0;
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reg_disable:
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stm32_usbphyc_regulators_disable(usbphyc);
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dec_n_pll_cons:
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atomic_dec(&usbphyc->n_pll_cons);
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return ret;
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}
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static int stm32_usbphyc_phy_init(struct phy *phy)
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{
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struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
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struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
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u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
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u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
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STM32_USBPHYC_MON_SEL_LOCKP);
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u32 monout;
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int ret;
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ret = stm32_usbphyc_pll_enable(usbphyc);
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if (ret)
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return ret;
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/* Check that PLL Lock input to PHY is High */
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writel_relaxed(monsel, usbphyc->base + reg_mon);
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ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
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(monout & STM32_USBPHYC_MON_OUT_LOCKP),
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100, 1000);
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if (ret) {
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dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
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(u32)(monout & STM32_USBPHYC_MON_OUT));
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goto pll_disable;
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}
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usbphyc_phy->active = true;
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return 0;
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pll_disable:
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return stm32_usbphyc_pll_disable(usbphyc);
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}
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static int stm32_usbphyc_phy_exit(struct phy *phy)
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{
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struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
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struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
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usbphyc_phy->active = false;
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return stm32_usbphyc_pll_disable(usbphyc);
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}
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static int stm32_usbphyc_phy_power_on(struct phy *phy)
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{
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struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
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if (usbphyc_phy->vbus)
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return regulator_enable(usbphyc_phy->vbus);
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return 0;
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}
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static int stm32_usbphyc_phy_power_off(struct phy *phy)
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{
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struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
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if (usbphyc_phy->vbus)
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return regulator_disable(usbphyc_phy->vbus);
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return 0;
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}
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static const struct phy_ops stm32_usbphyc_phy_ops = {
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.init = stm32_usbphyc_phy_init,
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.exit = stm32_usbphyc_phy_exit,
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.power_on = stm32_usbphyc_phy_power_on,
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.power_off = stm32_usbphyc_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
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{
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struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
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return stm32_usbphyc_pll_enable(usbphyc);
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}
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static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
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{
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struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
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stm32_usbphyc_pll_disable(usbphyc);
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}
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static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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return 48000000;
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}
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static const struct clk_ops usbphyc_clk48_ops = {
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.prepare = stm32_usbphyc_clk48_prepare,
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.unprepare = stm32_usbphyc_clk48_unprepare,
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.recalc_rate = stm32_usbphyc_clk48_recalc_rate,
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};
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static void stm32_usbphyc_clk48_unregister(void *data)
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{
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struct stm32_usbphyc *usbphyc = data;
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of_clk_del_provider(usbphyc->dev->of_node);
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clk_hw_unregister(&usbphyc->clk48_hw);
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}
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static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
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{
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struct device_node *node = usbphyc->dev->of_node;
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struct clk_init_data init = { };
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int ret = 0;
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init.name = "ck_usbo_48m";
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init.ops = &usbphyc_clk48_ops;
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usbphyc->clk48_hw.init = &init;
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ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
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if (ret)
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return ret;
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ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
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if (ret)
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clk_hw_unregister(&usbphyc->clk48_hw);
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return ret;
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}
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static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
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u32 utmi_switch)
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{
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if (!utmi_switch)
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stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
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SWITHOST);
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else
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stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
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SWITHOST);
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usbphyc->switch_setup = utmi_switch;
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}
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static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
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struct stm32_usbphyc_phy *usbphyc_phy = NULL;
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struct device_node *phynode = args->np;
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int port = 0;
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for (port = 0; port < usbphyc->nphys; port++) {
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if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
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usbphyc_phy = usbphyc->phys[port];
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break;
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}
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}
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if (!usbphyc_phy) {
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dev_err(dev, "failed to find phy\n");
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return ERR_PTR(-EINVAL);
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}
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if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
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((usbphyc_phy->index == 1) && (args->args_count != 1))) {
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dev_err(dev, "invalid number of cells for phy port%d\n",
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usbphyc_phy->index);
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return ERR_PTR(-EINVAL);
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}
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/* Configure the UTMI switch for PHY port#2 */
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if (usbphyc_phy->index == 1) {
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if (usbphyc->switch_setup < 0) {
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stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
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} else {
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if (args->args[0] != usbphyc->switch_setup) {
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dev_err(dev, "phy port1 already used\n");
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return ERR_PTR(-EBUSY);
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}
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}
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}
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return usbphyc_phy->phy;
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}
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static int stm32_usbphyc_probe(struct platform_device *pdev)
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{
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struct stm32_usbphyc *usbphyc;
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struct device *dev = &pdev->dev;
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struct device_node *child, *np = dev->of_node;
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struct phy_provider *phy_provider;
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u32 pllen, version;
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int ret, port = 0;
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usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
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if (!usbphyc)
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return -ENOMEM;
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usbphyc->dev = dev;
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dev_set_drvdata(dev, usbphyc);
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usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(usbphyc->base))
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return PTR_ERR(usbphyc->base);
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usbphyc->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(usbphyc->clk))
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return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
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ret = clk_prepare_enable(usbphyc->clk);
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if (ret) {
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dev_err(dev, "clk enable failed: %d\n", ret);
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return ret;
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}
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usbphyc->rst = devm_reset_control_get(dev, NULL);
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if (!IS_ERR(usbphyc->rst)) {
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reset_control_assert(usbphyc->rst);
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udelay(2);
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reset_control_deassert(usbphyc->rst);
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} else {
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ret = PTR_ERR(usbphyc->rst);
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if (ret == -EPROBE_DEFER)
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goto clk_disable;
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stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
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}
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/*
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* Wait for minimum width of powerdown pulse (ENABLE = Low):
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* we have to ensure the PLL is disabled before phys initialization.
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*/
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if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
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pllen, !(pllen & PLLEN), 5, 50)) {
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dev_warn(usbphyc->dev, "PLL not reset\n");
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ret = -EPROBE_DEFER;
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goto clk_disable;
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}
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usbphyc->switch_setup = -EINVAL;
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usbphyc->nphys = of_get_child_count(np);
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usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
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sizeof(*usbphyc->phys), GFP_KERNEL);
|
|
if (!usbphyc->phys) {
|
|
ret = -ENOMEM;
|
|
goto clk_disable;
|
|
}
|
|
|
|
usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
|
|
if (IS_ERR(usbphyc->vdda1v1)) {
|
|
ret = PTR_ERR(usbphyc->vdda1v1);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret);
|
|
goto clk_disable;
|
|
}
|
|
|
|
usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
|
|
if (IS_ERR(usbphyc->vdda1v8)) {
|
|
ret = PTR_ERR(usbphyc->vdda1v8);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret);
|
|
goto clk_disable;
|
|
}
|
|
|
|
for_each_child_of_node(np, child) {
|
|
struct stm32_usbphyc_phy *usbphyc_phy;
|
|
struct phy *phy;
|
|
u32 index;
|
|
|
|
phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
|
|
if (IS_ERR(phy)) {
|
|
ret = PTR_ERR(phy);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to create phy%d: %d\n",
|
|
port, ret);
|
|
goto put_child;
|
|
}
|
|
|
|
usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
|
|
GFP_KERNEL);
|
|
if (!usbphyc_phy) {
|
|
ret = -ENOMEM;
|
|
goto put_child;
|
|
}
|
|
|
|
ret = of_property_read_u32(child, "reg", &index);
|
|
if (ret || index > usbphyc->nphys) {
|
|
dev_err(&phy->dev, "invalid reg property: %d\n", ret);
|
|
goto put_child;
|
|
}
|
|
|
|
usbphyc->phys[port] = usbphyc_phy;
|
|
phy_set_bus_width(phy, 8);
|
|
phy_set_drvdata(phy, usbphyc_phy);
|
|
|
|
usbphyc->phys[port]->phy = phy;
|
|
usbphyc->phys[port]->usbphyc = usbphyc;
|
|
usbphyc->phys[port]->index = index;
|
|
usbphyc->phys[port]->active = false;
|
|
|
|
usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
|
|
if (IS_ERR(usbphyc->phys[port]->vbus)) {
|
|
ret = PTR_ERR(usbphyc->phys[port]->vbus);
|
|
if (ret == -EPROBE_DEFER)
|
|
goto put_child;
|
|
usbphyc->phys[port]->vbus = NULL;
|
|
}
|
|
|
|
port++;
|
|
}
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev,
|
|
stm32_usbphyc_of_xlate);
|
|
if (IS_ERR(phy_provider)) {
|
|
ret = PTR_ERR(phy_provider);
|
|
dev_err(dev, "failed to register phy provider: %d\n", ret);
|
|
goto clk_disable;
|
|
}
|
|
|
|
ret = stm32_usbphyc_clk48_register(usbphyc);
|
|
if (ret) {
|
|
dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
|
|
goto clk_disable;
|
|
}
|
|
|
|
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
|
|
dev_info(dev, "registered rev:%lu.%lu\n",
|
|
FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
|
|
|
|
return 0;
|
|
|
|
put_child:
|
|
of_node_put(child);
|
|
clk_disable:
|
|
clk_disable_unprepare(usbphyc->clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_usbphyc_remove(struct platform_device *pdev)
|
|
{
|
|
struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
|
|
int port;
|
|
|
|
/* Ensure PHYs are not active, to allow PLL disabling */
|
|
for (port = 0; port < usbphyc->nphys; port++)
|
|
if (usbphyc->phys[port]->active)
|
|
stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
|
|
|
|
stm32_usbphyc_clk48_unregister(usbphyc);
|
|
|
|
clk_disable_unprepare(usbphyc->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id stm32_usbphyc_of_match[] = {
|
|
{ .compatible = "st,stm32mp1-usbphyc", },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
|
|
|
|
static struct platform_driver stm32_usbphyc_driver = {
|
|
.probe = stm32_usbphyc_probe,
|
|
.remove = stm32_usbphyc_remove,
|
|
.driver = {
|
|
.of_match_table = stm32_usbphyc_of_match,
|
|
.name = "stm32-usbphyc",
|
|
}
|
|
};
|
|
module_platform_driver(stm32_usbphyc_driver);
|
|
|
|
MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
|
|
MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
|
|
MODULE_LICENSE("GPL v2");
|