220 lines
5.1 KiB
C
220 lines
5.1 KiB
C
/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#define PCIE_CFG_OFFSET 0x00
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#define PCIE1_PHY_IDDQ_SHIFT 10
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#define PCIE0_PHY_IDDQ_SHIFT 2
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enum cygnus_pcie_phy_id {
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CYGNUS_PHY_PCIE0 = 0,
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CYGNUS_PHY_PCIE1,
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MAX_NUM_PHYS,
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};
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struct cygnus_pcie_phy_core;
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/**
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* struct cygnus_pcie_phy - Cygnus PCIe PHY device
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* @core: pointer to the Cygnus PCIe PHY core control
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* @id: internal ID to identify the Cygnus PCIe PHY
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* @phy: pointer to the kernel PHY device
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*/
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struct cygnus_pcie_phy {
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struct cygnus_pcie_phy_core *core;
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enum cygnus_pcie_phy_id id;
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struct phy *phy;
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};
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/**
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* struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
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* @dev: pointer to device
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* @base: base register
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* @lock: mutex to protect access to individual PHYs
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* @phys: pointer to Cygnus PHY device
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*/
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struct cygnus_pcie_phy_core {
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struct device *dev;
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void __iomem *base;
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struct mutex lock;
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struct cygnus_pcie_phy phys[MAX_NUM_PHYS];
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};
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static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable)
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{
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struct cygnus_pcie_phy_core *core = phy->core;
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unsigned shift;
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u32 val;
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mutex_lock(&core->lock);
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switch (phy->id) {
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case CYGNUS_PHY_PCIE0:
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shift = PCIE0_PHY_IDDQ_SHIFT;
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break;
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case CYGNUS_PHY_PCIE1:
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shift = PCIE1_PHY_IDDQ_SHIFT;
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break;
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default:
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mutex_unlock(&core->lock);
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dev_err(core->dev, "PCIe PHY %d invalid\n", phy->id);
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return -EINVAL;
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}
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if (enable) {
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val = readl(core->base + PCIE_CFG_OFFSET);
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val &= ~BIT(shift);
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writel(val, core->base + PCIE_CFG_OFFSET);
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/*
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* Wait 50 ms for the PCIe Serdes to stabilize after the analog
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* front end is brought up
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*/
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msleep(50);
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} else {
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val = readl(core->base + PCIE_CFG_OFFSET);
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val |= BIT(shift);
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writel(val, core->base + PCIE_CFG_OFFSET);
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}
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mutex_unlock(&core->lock);
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dev_dbg(core->dev, "PCIe PHY %d %s\n", phy->id,
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enable ? "enabled" : "disabled");
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return 0;
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}
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static int cygnus_pcie_phy_power_on(struct phy *p)
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{
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struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
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return cygnus_pcie_power_config(phy, true);
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}
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static int cygnus_pcie_phy_power_off(struct phy *p)
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{
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struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
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return cygnus_pcie_power_config(phy, false);
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}
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static const struct phy_ops cygnus_pcie_phy_ops = {
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.power_on = cygnus_pcie_phy_power_on,
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.power_off = cygnus_pcie_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int cygnus_pcie_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node, *child;
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struct cygnus_pcie_phy_core *core;
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struct phy_provider *provider;
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unsigned cnt = 0;
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int ret;
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if (of_get_child_count(node) == 0) {
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dev_err(dev, "PHY no child node\n");
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return -ENODEV;
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}
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core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
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if (!core)
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return -ENOMEM;
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core->dev = dev;
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core->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(core->base))
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return PTR_ERR(core->base);
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mutex_init(&core->lock);
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for_each_available_child_of_node(node, child) {
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unsigned int id;
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struct cygnus_pcie_phy *p;
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if (of_property_read_u32(child, "reg", &id)) {
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dev_err(dev, "missing reg property for %pOFn\n",
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child);
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ret = -EINVAL;
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goto put_child;
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}
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if (id >= MAX_NUM_PHYS) {
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dev_err(dev, "invalid PHY id: %u\n", id);
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ret = -EINVAL;
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goto put_child;
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}
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if (core->phys[id].phy) {
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dev_err(dev, "duplicated PHY id: %u\n", id);
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ret = -EINVAL;
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goto put_child;
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}
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p = &core->phys[id];
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p->phy = devm_phy_create(dev, child, &cygnus_pcie_phy_ops);
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if (IS_ERR(p->phy)) {
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dev_err(dev, "failed to create PHY\n");
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ret = PTR_ERR(p->phy);
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goto put_child;
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}
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p->core = core;
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p->id = id;
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phy_set_drvdata(p->phy, p);
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cnt++;
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}
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dev_set_drvdata(dev, core);
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(provider)) {
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dev_err(dev, "failed to register PHY provider\n");
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return PTR_ERR(provider);
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}
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dev_dbg(dev, "registered %u PCIe PHY(s)\n", cnt);
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return 0;
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put_child:
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of_node_put(child);
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return ret;
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}
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static const struct of_device_id cygnus_pcie_phy_match_table[] = {
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{ .compatible = "brcm,cygnus-pcie-phy" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, cygnus_pcie_phy_match_table);
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static struct platform_driver cygnus_pcie_phy_driver = {
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.driver = {
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.name = "cygnus-pcie-phy",
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.of_match_table = cygnus_pcie_phy_match_table,
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},
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.probe = cygnus_pcie_phy_probe,
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};
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module_platform_driver(cygnus_pcie_phy_driver);
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MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom Cygnus PCIe PHY driver");
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MODULE_LICENSE("GPL v2");
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