150 lines
3.6 KiB
C
150 lines
3.6 KiB
C
/*
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* arch/arm/mach-dove/addr-map.c
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*
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* Address map functions for Marvell Dove 88AP510 SoC
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <asm/mach/arch.h>
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#include <asm/setup.h>
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#include "common.h"
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DDR 0x0
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#define TARGET_BOOTROM 0x1
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#define TARGET_CESA 0x3
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#define TARGET_PCIE0 0x4
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#define TARGET_PCIE1 0x8
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#define TARGET_SCRATCHPAD 0xd
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#define ATTR_CESA 0x01
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#define ATTR_BOOTROM 0xfd
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#define ATTR_DEV_SPI0_ROM 0xfe
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#define ATTR_DEV_SPI1_ROM 0xfb
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#define ATTR_PCIE_IO 0xe0
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#define ATTR_PCIE_MEM 0xe8
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#define ATTR_SCRATCHPAD 0x0
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/*
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* CPU Address Decode Windows registers
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*/
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#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
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#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
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#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
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#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
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struct mbus_dram_target_info dove_mbus_dram_info;
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static inline void __iomem *ddr_map_sc(int i)
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{
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return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
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}
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static int cpu_win_can_remap(int win)
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{
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if (win < 4)
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return 1;
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return 0;
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}
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static void __init setup_cpu_win(int win, u32 base, u32 size,
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u8 target, u8 attr, int remap)
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{
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u32 ctrl;
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base &= 0xffff0000;
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ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
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writel(base, WIN_BASE(win));
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writel(ctrl, WIN_CTRL(win));
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if (cpu_win_can_remap(win)) {
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if (remap < 0)
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remap = base;
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writel(remap & 0xffff0000, WIN_REMAP_LO(win));
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writel(0, WIN_REMAP_HI(win));
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}
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}
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void __init dove_setup_cpu_mbus(void)
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{
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int i;
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int cs;
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/*
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* First, disable and clear windows.
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*/
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for (i = 0; i < 8; i++) {
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writel(0, WIN_BASE(i));
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writel(0, WIN_CTRL(i));
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if (cpu_win_can_remap(i)) {
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writel(0, WIN_REMAP_LO(i));
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writel(0, WIN_REMAP_HI(i));
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}
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}
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/*
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* Setup windows for PCIe IO+MEM space.
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*/
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setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
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TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE);
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setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
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TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
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setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
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TARGET_PCIE0, ATTR_PCIE_MEM, -1);
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setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
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TARGET_PCIE1, ATTR_PCIE_MEM, -1);
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/*
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* Setup window for CESA engine.
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*/
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setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
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TARGET_CESA, ATTR_CESA, -1);
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/*
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* Setup the Window to the BootROM for Standby and Sleep Resume
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*/
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setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
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TARGET_BOOTROM, ATTR_BOOTROM, -1);
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/*
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* Setup the Window to the PMU Scratch Pad space
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*/
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setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
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TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
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/*
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* Setup MBUS dram target info.
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*/
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dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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for (i = 0, cs = 0; i < 2; i++) {
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u32 map = readl(ddr_map_sc(i));
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/*
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* Chip select enabled?
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*/
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if (map & 1) {
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struct mbus_dram_window *w;
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w = &dove_mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0; /* CS address decoding done inside */
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/* the DDR controller, no need to */
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/* provide attributes */
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w->base = map & 0xff800000;
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w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
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}
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}
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dove_mbus_dram_info.num_cs = cs;
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}
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