Jerome Brunet 513b67ac39 clk: meson: add mpll pre-divider ... mpll clocks parent can actually be divided by 1 or 2. So far, this divider has always been set to 1, so the calculation was correct. Now that we know it exists, model the tree correctly. If we ever get a platform where the divider is different, we won't get into trouble Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>		2018-03-13 10:09:56 +01:00
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Kconfig	clk: meson: use hhi syscon if available	2018-03-13 10:04:04 +01:00
Makefile	clk: meson: remove obsolete cpu_clk	2018-03-13 10:04:04 +01:00
axg.c	clk: meson: add mpll pre-divider	2018-03-13 10:09:56 +01:00
axg.h	clk: meson: add mpll pre-divider	2018-03-13 10:09:56 +01:00
clk-audio-divider.c	clk: meson: migrate the audio divider clock to clk_regmap	2018-03-13 10:04:02 +01:00
clk-mpll.c	clk: meson: split divider and gate part of mpll	2018-03-13 10:04:03 +01:00
clk-pll.c	clk: meson: add ROUND_CLOSEST to the pll driver	2018-03-13 10:09:49 +01:00
clk-regmap.c	clk: meson: add regmap clocks	2018-03-13 10:03:58 +01:00
clk-regmap.h	clk: meson: add regmap clocks	2018-03-13 10:03:58 +01:00
clkc.h	clk: meson: add ROUND_CLOSEST to the pll driver	2018-03-13 10:09:49 +01:00
gxbb-aoclk-32k.c	clk: meson: gxbb-aoclk: Add CEC 32k clock	2017-08-04 18:02:02 +02:00
gxbb-aoclk.c	clk: meson: switch gxbb ao_clk to clk_regmap	2018-03-13 10:03:59 +01:00
gxbb-aoclk.h	clk: meson: remove superseded aoclk_gate_regmap	2018-03-13 10:03:59 +01:00
gxbb.c	clk: meson: add mpll pre-divider	2018-03-13 10:09:56 +01:00
gxbb.h	clk: meson: add mpll pre-divider	2018-03-13 10:09:56 +01:00
meson8b.c	clk: meson: add mpll pre-divider	2018-03-13 10:09:56 +01:00
meson8b.h	clk: meson: add mpll pre-divider	2018-03-13 10:09:56 +01:00