55 lines
1.7 KiB
Plaintext
55 lines
1.7 KiB
Plaintext
* Renesas RZ Clock Pulse Generator (CPG)
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The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
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CPU and GPU clocks, and several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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- compatible: Must be one of
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- "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
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and "renesas,rz-cpg-clocks" as a fallback.
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: References to possible parent clocks. Order must match clock modes
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in the datasheet. For the r7s72100, this is extal, usb_x1.
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "pll",
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"i", and "g"
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@fcfe0000 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-cpg-clocks",
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"renesas,rz-cpg-clocks";
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reg = <0xfcfe0000 0x18>;
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clocks = <&extal_clk>, <&usb_x1_clk>;
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clock-output-names = "pll", "i", "g";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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mtu2: timer@fcff0000 {
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compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
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reg = <0xfcff0000 0x400>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tgi0a";
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clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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