600 lines
16 KiB
C
600 lines
16 KiB
C
/*
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* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
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* VA Linux Systems Inc., Fremont, California.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Original Authors:
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* Kevin E. Martin, Rickard E. Faith, Alan Hourihane
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*
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* Kernel port Author: Dave Airlie
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*/
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#ifndef AMDGPU_MODE_H
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#define AMDGPU_MODE_H
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_fixed.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/hrtimer.h>
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#include "amdgpu_irq.h"
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struct amdgpu_bo;
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struct amdgpu_device;
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struct amdgpu_encoder;
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struct amdgpu_router;
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struct amdgpu_hpd;
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#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
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#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
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#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
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#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
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#define AMDGPU_MAX_HPD_PINS 6
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#define AMDGPU_MAX_CRTCS 6
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#define AMDGPU_MAX_AFMT_BLOCKS 9
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enum amdgpu_rmx_type {
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RMX_OFF,
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RMX_FULL,
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RMX_CENTER,
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RMX_ASPECT
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};
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enum amdgpu_underscan_type {
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UNDERSCAN_OFF,
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UNDERSCAN_ON,
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UNDERSCAN_AUTO,
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};
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#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
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#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
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enum amdgpu_hpd_id {
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AMDGPU_HPD_1 = 0,
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AMDGPU_HPD_2,
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AMDGPU_HPD_3,
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AMDGPU_HPD_4,
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AMDGPU_HPD_5,
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AMDGPU_HPD_6,
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AMDGPU_HPD_LAST,
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AMDGPU_HPD_NONE = 0xff,
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};
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enum amdgpu_crtc_irq {
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AMDGPU_CRTC_IRQ_VBLANK1 = 0,
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AMDGPU_CRTC_IRQ_VBLANK2,
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AMDGPU_CRTC_IRQ_VBLANK3,
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AMDGPU_CRTC_IRQ_VBLANK4,
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AMDGPU_CRTC_IRQ_VBLANK5,
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AMDGPU_CRTC_IRQ_VBLANK6,
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AMDGPU_CRTC_IRQ_VLINE1,
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AMDGPU_CRTC_IRQ_VLINE2,
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AMDGPU_CRTC_IRQ_VLINE3,
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AMDGPU_CRTC_IRQ_VLINE4,
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AMDGPU_CRTC_IRQ_VLINE5,
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AMDGPU_CRTC_IRQ_VLINE6,
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AMDGPU_CRTC_IRQ_LAST,
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AMDGPU_CRTC_IRQ_NONE = 0xff
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};
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enum amdgpu_pageflip_irq {
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AMDGPU_PAGEFLIP_IRQ_D1 = 0,
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AMDGPU_PAGEFLIP_IRQ_D2,
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AMDGPU_PAGEFLIP_IRQ_D3,
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AMDGPU_PAGEFLIP_IRQ_D4,
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AMDGPU_PAGEFLIP_IRQ_D5,
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AMDGPU_PAGEFLIP_IRQ_D6,
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AMDGPU_PAGEFLIP_IRQ_LAST,
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AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
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};
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enum amdgpu_flip_status {
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AMDGPU_FLIP_NONE,
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AMDGPU_FLIP_PENDING,
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AMDGPU_FLIP_SUBMITTED
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};
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#define AMDGPU_MAX_I2C_BUS 16
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/* amdgpu gpio-based i2c
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* 1. "mask" reg and bits
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* grabs the gpio pins for software use
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* 0=not held 1=held
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* 2. "a" reg and bits
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* output pin value
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* 0=low 1=high
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* 3. "en" reg and bits
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* sets the pin direction
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* 0=input 1=output
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* 4. "y" reg and bits
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* input pin value
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* 0=low 1=high
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*/
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struct amdgpu_i2c_bus_rec {
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bool valid;
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/* id used by atom */
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uint8_t i2c_id;
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/* id used by atom */
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enum amdgpu_hpd_id hpd;
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/* can be used with hw i2c engine */
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bool hw_capable;
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/* uses multi-media i2c engine */
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bool mm_i2c;
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/* regs and bits */
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uint32_t mask_clk_reg;
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uint32_t mask_data_reg;
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uint32_t a_clk_reg;
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uint32_t a_data_reg;
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uint32_t en_clk_reg;
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uint32_t en_data_reg;
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uint32_t y_clk_reg;
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uint32_t y_data_reg;
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uint32_t mask_clk_mask;
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uint32_t mask_data_mask;
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uint32_t a_clk_mask;
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uint32_t a_data_mask;
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uint32_t en_clk_mask;
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uint32_t en_data_mask;
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uint32_t y_clk_mask;
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uint32_t y_data_mask;
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};
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#define AMDGPU_MAX_BIOS_CONNECTOR 16
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/* pll flags */
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#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
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#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
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#define AMDGPU_PLL_USE_REF_DIV (1 << 2)
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#define AMDGPU_PLL_LEGACY (1 << 3)
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#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
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#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
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#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
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#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
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#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
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#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
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#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
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#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
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#define AMDGPU_PLL_USE_POST_DIV (1 << 12)
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#define AMDGPU_PLL_IS_LCD (1 << 13)
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#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
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struct amdgpu_pll {
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/* reference frequency */
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uint32_t reference_freq;
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/* fixed dividers */
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uint32_t reference_div;
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uint32_t post_div;
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/* pll in/out limits */
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uint32_t pll_in_min;
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uint32_t pll_in_max;
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uint32_t pll_out_min;
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uint32_t pll_out_max;
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uint32_t lcd_pll_out_min;
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uint32_t lcd_pll_out_max;
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uint32_t best_vco;
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/* divider limits */
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uint32_t min_ref_div;
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uint32_t max_ref_div;
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uint32_t min_post_div;
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uint32_t max_post_div;
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uint32_t min_feedback_div;
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uint32_t max_feedback_div;
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uint32_t min_frac_feedback_div;
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uint32_t max_frac_feedback_div;
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/* flags for the current clock */
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uint32_t flags;
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/* pll id */
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uint32_t id;
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};
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struct amdgpu_i2c_chan {
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struct i2c_adapter adapter;
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struct drm_device *dev;
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struct i2c_algo_bit_data bit;
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struct amdgpu_i2c_bus_rec rec;
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struct drm_dp_aux aux;
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bool has_aux;
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struct mutex mutex;
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};
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struct amdgpu_fbdev;
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struct amdgpu_afmt {
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bool enabled;
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int offset;
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bool last_buffer_filled_status;
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int id;
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struct amdgpu_audio_pin *pin;
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};
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/*
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* Audio
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*/
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struct amdgpu_audio_pin {
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int channels;
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int rate;
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int bits_per_sample;
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u8 status_bits;
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u8 category_code;
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u32 offset;
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bool connected;
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u32 id;
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};
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struct amdgpu_audio {
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bool enabled;
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struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
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int num_pins;
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};
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struct amdgpu_mode_mc_save {
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u32 vga_render_control;
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u32 vga_hdp_control;
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bool crtc_enabled[AMDGPU_MAX_CRTCS];
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};
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struct amdgpu_display_funcs {
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/* vga render */
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void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
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/* display watermarks */
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void (*bandwidth_update)(struct amdgpu_device *adev);
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/* get frame count */
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u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
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/* wait for vblank */
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void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
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/* set backlight level */
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void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
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u8 level);
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/* get backlight level */
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u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
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/* hotplug detect */
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bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
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void (*hpd_set_polarity)(struct amdgpu_device *adev,
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enum amdgpu_hpd_id hpd);
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u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
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/* pageflipping */
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void (*page_flip)(struct amdgpu_device *adev,
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int crtc_id, u64 crtc_base, bool async);
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int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
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u32 *vbl, u32 *position);
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/* display topology setup */
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void (*add_encoder)(struct amdgpu_device *adev,
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uint32_t encoder_enum,
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uint32_t supported_device,
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u16 caps);
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void (*add_connector)(struct amdgpu_device *adev,
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uint32_t connector_id,
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uint32_t supported_device,
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int connector_type,
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struct amdgpu_i2c_bus_rec *i2c_bus,
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uint16_t connector_object_id,
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struct amdgpu_hpd *hpd,
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struct amdgpu_router *router);
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void (*stop_mc_access)(struct amdgpu_device *adev,
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struct amdgpu_mode_mc_save *save);
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void (*resume_mc_access)(struct amdgpu_device *adev,
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struct amdgpu_mode_mc_save *save);
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};
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struct amdgpu_mode_info {
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struct atom_context *atom_context;
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struct card_info *atom_card_info;
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bool mode_config_initialized;
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struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
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struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
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/* DVI-I properties */
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struct drm_property *coherent_mode_property;
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/* DAC enable load detect */
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struct drm_property *load_detect_property;
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/* underscan */
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struct drm_property *underscan_property;
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struct drm_property *underscan_hborder_property;
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struct drm_property *underscan_vborder_property;
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/* audio */
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struct drm_property *audio_property;
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/* FMT dithering */
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struct drm_property *dither_property;
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/* hardcoded DFP edid from BIOS */
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struct edid *bios_hardcoded_edid;
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int bios_hardcoded_edid_size;
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/* pointer to fbdev info structure */
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struct amdgpu_fbdev *rfbdev;
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/* firmware flags */
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u16 firmware_flags;
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/* pointer to backlight encoder */
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struct amdgpu_encoder *bl_encoder;
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struct amdgpu_audio audio; /* audio stuff */
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int num_crtc; /* number of crtcs */
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int num_hpd; /* number of hpd pins */
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int num_dig; /* number of dig blocks */
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int disp_priority;
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const struct amdgpu_display_funcs *funcs;
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};
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#define AMDGPU_MAX_BL_LEVEL 0xFF
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#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
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struct amdgpu_backlight_privdata {
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struct amdgpu_encoder *encoder;
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uint8_t negative;
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};
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#endif
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struct amdgpu_atom_ss {
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uint16_t percentage;
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uint16_t percentage_divider;
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uint8_t type;
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uint16_t step;
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uint8_t delay;
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uint8_t range;
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uint8_t refdiv;
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/* asic_ss */
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uint16_t rate;
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uint16_t amount;
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};
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struct amdgpu_crtc {
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struct drm_crtc base;
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int crtc_id;
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u16 lut_r[256], lut_g[256], lut_b[256];
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bool enabled;
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bool can_tile;
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uint32_t crtc_offset;
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struct drm_gem_object *cursor_bo;
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uint64_t cursor_addr;
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int cursor_x;
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int cursor_y;
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int cursor_hot_x;
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int cursor_hot_y;
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int cursor_width;
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int cursor_height;
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int max_cursor_width;
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int max_cursor_height;
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enum amdgpu_rmx_type rmx_type;
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u8 h_border;
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u8 v_border;
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fixed20_12 vsc;
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fixed20_12 hsc;
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struct drm_display_mode native_mode;
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u32 pll_id;
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/* page flipping */
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struct amdgpu_flip_work *pflip_works;
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enum amdgpu_flip_status pflip_status;
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int deferred_flip_completion;
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/* pll sharing */
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struct amdgpu_atom_ss ss;
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bool ss_enabled;
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u32 adjusted_clock;
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int bpc;
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u32 pll_reference_div;
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u32 pll_post_div;
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u32 pll_flags;
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struct drm_encoder *encoder;
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struct drm_connector *connector;
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/* for dpm */
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u32 line_time;
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u32 wm_low;
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u32 wm_high;
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u32 lb_vblank_lead_lines;
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struct drm_display_mode hw_mode;
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/* for virtual dce */
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struct hrtimer vblank_timer;
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enum amdgpu_interrupt_state vsync_timer_enabled;
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};
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struct amdgpu_encoder_atom_dig {
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bool linkb;
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/* atom dig */
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bool coherent_mode;
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int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
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/* atom lvds/edp */
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uint32_t lcd_misc;
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uint16_t panel_pwr_delay;
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uint32_t lcd_ss_id;
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/* panel mode */
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struct drm_display_mode native_mode;
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struct backlight_device *bl_dev;
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int dpms_mode;
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uint8_t backlight_level;
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int panel_mode;
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struct amdgpu_afmt *afmt;
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};
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struct amdgpu_encoder {
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struct drm_encoder base;
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uint32_t encoder_enum;
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uint32_t encoder_id;
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uint32_t devices;
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uint32_t active_device;
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uint32_t flags;
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uint32_t pixel_clock;
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enum amdgpu_rmx_type rmx_type;
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enum amdgpu_underscan_type underscan_type;
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uint32_t underscan_hborder;
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uint32_t underscan_vborder;
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struct drm_display_mode native_mode;
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void *enc_priv;
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int audio_polling_active;
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bool is_ext_encoder;
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u16 caps;
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};
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struct amdgpu_connector_atom_dig {
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/* displayport */
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u8 dpcd[DP_RECEIVER_CAP_SIZE];
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u8 dp_sink_type;
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int dp_clock;
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int dp_lane_count;
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bool edp_on;
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};
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struct amdgpu_gpio_rec {
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bool valid;
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u8 id;
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u32 reg;
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u32 mask;
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u32 shift;
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};
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struct amdgpu_hpd {
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enum amdgpu_hpd_id hpd;
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u8 plugged_state;
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struct amdgpu_gpio_rec gpio;
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};
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struct amdgpu_router {
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u32 router_id;
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struct amdgpu_i2c_bus_rec i2c_info;
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u8 i2c_addr;
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/* i2c mux */
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bool ddc_valid;
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u8 ddc_mux_type;
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u8 ddc_mux_control_pin;
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u8 ddc_mux_state;
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/* clock/data mux */
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bool cd_valid;
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u8 cd_mux_type;
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u8 cd_mux_control_pin;
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u8 cd_mux_state;
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};
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enum amdgpu_connector_audio {
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AMDGPU_AUDIO_DISABLE = 0,
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AMDGPU_AUDIO_ENABLE = 1,
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AMDGPU_AUDIO_AUTO = 2
|
|
};
|
|
|
|
enum amdgpu_connector_dither {
|
|
AMDGPU_FMT_DITHER_DISABLE = 0,
|
|
AMDGPU_FMT_DITHER_ENABLE = 1,
|
|
};
|
|
|
|
struct amdgpu_connector {
|
|
struct drm_connector base;
|
|
uint32_t connector_id;
|
|
uint32_t devices;
|
|
struct amdgpu_i2c_chan *ddc_bus;
|
|
/* some systems have an hdmi and vga port with a shared ddc line */
|
|
bool shared_ddc;
|
|
bool use_digital;
|
|
/* we need to mind the EDID between detect
|
|
and get modes due to analog/digital/tvencoder */
|
|
struct edid *edid;
|
|
void *con_priv;
|
|
bool dac_load_detect;
|
|
bool detected_by_load; /* if the connection status was determined by load */
|
|
uint16_t connector_object_id;
|
|
struct amdgpu_hpd hpd;
|
|
struct amdgpu_router router;
|
|
struct amdgpu_i2c_chan *router_bus;
|
|
enum amdgpu_connector_audio audio;
|
|
enum amdgpu_connector_dither dither;
|
|
unsigned pixelclock_for_modeset;
|
|
};
|
|
|
|
struct amdgpu_framebuffer {
|
|
struct drm_framebuffer base;
|
|
struct drm_gem_object *obj;
|
|
};
|
|
|
|
#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
|
|
((em) == ATOM_ENCODER_MODE_DP_MST))
|
|
|
|
/* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
|
|
#define USE_REAL_VBLANKSTART (1 << 30)
|
|
#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
|
|
|
|
void amdgpu_link_encoder_connector(struct drm_device *dev);
|
|
|
|
struct drm_connector *
|
|
amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
|
|
struct drm_connector *
|
|
amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
|
|
bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
|
|
u32 pixel_clock);
|
|
|
|
u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
|
|
struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
|
|
|
|
bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
|
|
|
|
void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
|
|
|
|
int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
|
|
unsigned int flags, int *vpos, int *hpos,
|
|
ktime_t *stime, ktime_t *etime,
|
|
const struct drm_display_mode *mode);
|
|
|
|
int amdgpu_framebuffer_init(struct drm_device *dev,
|
|
struct amdgpu_framebuffer *rfb,
|
|
const struct drm_mode_fb_cmd2 *mode_cmd,
|
|
struct drm_gem_object *obj);
|
|
|
|
int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
|
|
|
|
void amdgpu_enc_destroy(struct drm_encoder *encoder);
|
|
void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
|
|
bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
|
|
const struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode);
|
|
void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
|
|
struct drm_display_mode *adjusted_mode);
|
|
int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
|
|
|
|
/* fbdev layer */
|
|
int amdgpu_fbdev_init(struct amdgpu_device *adev);
|
|
void amdgpu_fbdev_fini(struct amdgpu_device *adev);
|
|
void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
|
|
int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
|
|
bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
|
|
void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);
|
|
|
|
void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
|
|
|
|
|
|
int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
|
|
|
|
/* amdgpu_display.c */
|
|
void amdgpu_print_display_setup(struct drm_device *dev);
|
|
int amdgpu_modeset_create_props(struct amdgpu_device *adev);
|
|
int amdgpu_crtc_set_config(struct drm_mode_set *set);
|
|
int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb,
|
|
struct drm_pending_vblank_event *event,
|
|
uint32_t page_flip_flags, uint32_t target);
|
|
extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
|
|
|
|
#endif
|