490 lines
12 KiB
C
490 lines
12 KiB
C
/*
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* Intel MID GPIO driver
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*
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* Copyright (c) 2008-2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Supports:
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* Moorestown platform Langwell chip.
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* Medfield platform Penwell chip.
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* Clovertrail platform Cloverview chip.
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* Merrifield platform Tangier chip.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/stddef.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/irqdomain.h>
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#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
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#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
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/*
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* Langwell chip has 64 pins and thus there are 2 32bit registers to control
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* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
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* registers to control them, so we only define the order here instead of a
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* structure, to get a bit offset for a pin (use GPDR as an example):
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*
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* nreg = ngpio / 32;
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* reg = offset / 32;
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* bit = offset % 32;
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* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
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*
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* so the bit of reg_addr is to control pin offset's GPDR feature
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*/
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enum GPIO_REG {
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GPLR = 0, /* pin level read-only */
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GPDR, /* pin direction */
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GPSR, /* pin set */
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GPCR, /* pin clear */
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GRER, /* rising edge detect */
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GFER, /* falling edge detect */
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GEDR, /* edge detect result */
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GAFR, /* alt function */
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};
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/* intel_mid gpio driver data */
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struct intel_mid_gpio_ddata {
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u16 ngpio; /* number of gpio pins */
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u32 gplr_offset; /* offset of first GPLR register from base */
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u32 flis_base; /* base address of FLIS registers */
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u32 flis_len; /* length of FLIS registers */
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u32 (*get_flis_offset)(int gpio);
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u32 chip_irq_type; /* chip interrupt type */
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};
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struct intel_mid_gpio {
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struct gpio_chip chip;
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void __iomem *reg_base;
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spinlock_t lock;
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struct pci_dev *pdev;
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struct irq_domain *domain;
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};
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#define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)
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static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
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enum GPIO_REG reg_type)
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{
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struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
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unsigned nreg = chip->ngpio / 32;
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u8 reg = offset / 32;
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return priv->reg_base + reg_type * nreg * 4 + reg * 4;
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}
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static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
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enum GPIO_REG reg_type)
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{
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struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
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unsigned nreg = chip->ngpio / 32;
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u8 reg = offset / 16;
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return priv->reg_base + reg_type * nreg * 4 + reg * 4;
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}
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static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
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u32 value = readl(gafr);
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int shift = (offset % 16) << 1, af = (value >> shift) & 3;
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if (af) {
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value &= ~(3 << shift);
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writel(value, gafr);
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}
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return 0;
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}
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static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *gplr = gpio_reg(chip, offset, GPLR);
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return readl(gplr) & BIT(offset % 32);
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}
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static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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void __iomem *gpsr, *gpcr;
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if (value) {
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gpsr = gpio_reg(chip, offset, GPSR);
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writel(BIT(offset % 32), gpsr);
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} else {
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gpcr = gpio_reg(chip, offset, GPCR);
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writel(BIT(offset % 32), gpcr);
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}
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}
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static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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u32 value;
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unsigned long flags;
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if (priv->pdev)
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pm_runtime_get(&priv->pdev->dev);
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spin_lock_irqsave(&priv->lock, flags);
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value = readl(gpdr);
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value &= ~BIT(offset % 32);
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writel(value, gpdr);
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spin_unlock_irqrestore(&priv->lock, flags);
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if (priv->pdev)
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pm_runtime_put(&priv->pdev->dev);
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return 0;
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}
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static int intel_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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unsigned long flags;
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intel_gpio_set(chip, offset, value);
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if (priv->pdev)
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pm_runtime_get(&priv->pdev->dev);
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spin_lock_irqsave(&priv->lock, flags);
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value = readl(gpdr);
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value |= BIT(offset % 32);
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writel(value, gpdr);
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spin_unlock_irqrestore(&priv->lock, flags);
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if (priv->pdev)
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pm_runtime_put(&priv->pdev->dev);
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return 0;
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}
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static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
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return irq_create_mapping(priv->domain, offset);
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}
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static int intel_mid_irq_type(struct irq_data *d, unsigned type)
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{
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struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
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u32 gpio = irqd_to_hwirq(d);
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unsigned long flags;
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u32 value;
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void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
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void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
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if (gpio >= priv->chip.ngpio)
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return -EINVAL;
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if (priv->pdev)
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pm_runtime_get(&priv->pdev->dev);
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spin_lock_irqsave(&priv->lock, flags);
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if (type & IRQ_TYPE_EDGE_RISING)
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value = readl(grer) | BIT(gpio % 32);
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else
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value = readl(grer) & (~BIT(gpio % 32));
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writel(value, grer);
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if (type & IRQ_TYPE_EDGE_FALLING)
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value = readl(gfer) | BIT(gpio % 32);
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else
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value = readl(gfer) & (~BIT(gpio % 32));
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writel(value, gfer);
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spin_unlock_irqrestore(&priv->lock, flags);
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if (priv->pdev)
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pm_runtime_put(&priv->pdev->dev);
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return 0;
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}
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static void intel_mid_irq_unmask(struct irq_data *d)
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{
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}
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static void intel_mid_irq_mask(struct irq_data *d)
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{
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}
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static int intel_mid_irq_reqres(struct irq_data *d)
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{
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struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
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if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d))) {
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dev_err(priv->chip.dev,
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"unable to lock HW IRQ %lu for IRQ\n",
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irqd_to_hwirq(d));
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return -EINVAL;
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}
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return 0;
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}
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static void intel_mid_irq_relres(struct irq_data *d)
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{
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struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
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gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d));
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}
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static struct irq_chip intel_mid_irqchip = {
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.name = "INTEL_MID-GPIO",
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.irq_mask = intel_mid_irq_mask,
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.irq_unmask = intel_mid_irq_unmask,
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.irq_set_type = intel_mid_irq_type,
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.irq_request_resources = intel_mid_irq_reqres,
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.irq_release_resources = intel_mid_irq_relres,
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};
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static const struct intel_mid_gpio_ddata gpio_lincroft = {
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.ngpio = 64,
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};
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static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
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.ngpio = 96,
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.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
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};
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static const struct intel_mid_gpio_ddata gpio_penwell_core = {
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.ngpio = 96,
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.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
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};
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static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
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.ngpio = 96,
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.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
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};
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static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
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.ngpio = 96,
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.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
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};
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static const struct intel_mid_gpio_ddata gpio_tangier = {
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.ngpio = 192,
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.gplr_offset = 4,
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.flis_base = 0xff0c0000,
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.flis_len = 0x8000,
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.get_flis_offset = NULL,
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.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
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};
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static const struct pci_device_id intel_gpio_ids[] = {
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{
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/* Lincroft */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
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.driver_data = (kernel_ulong_t)&gpio_lincroft,
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},
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{
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/* Penwell AON */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
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.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
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},
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{
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/* Penwell Core */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
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.driver_data = (kernel_ulong_t)&gpio_penwell_core,
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},
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{
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/* Cloverview Aon */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
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.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
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},
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{
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/* Cloverview Core */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
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.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
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},
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{
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/* Tangier */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
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.driver_data = (kernel_ulong_t)&gpio_tangier,
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},
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{ 0 }
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};
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MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
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static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct irq_data *data = irq_desc_get_irq_data(desc);
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struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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u32 base, gpio, mask;
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unsigned long pending;
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void __iomem *gedr;
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/* check GPIO controller to check which pin triggered the interrupt */
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for (base = 0; base < priv->chip.ngpio; base += 32) {
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gedr = gpio_reg(&priv->chip, base, GEDR);
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while ((pending = readl(gedr))) {
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gpio = __ffs(pending);
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mask = BIT(gpio);
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/* Clear before handling so we can't lose an edge */
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writel(mask, gedr);
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generic_handle_irq(irq_find_mapping(priv->domain,
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base + gpio));
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}
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}
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chip->irq_eoi(data);
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}
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static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
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{
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void __iomem *reg;
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unsigned base;
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for (base = 0; base < priv->chip.ngpio; base += 32) {
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/* Clear the rising-edge detect register */
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reg = gpio_reg(&priv->chip, base, GRER);
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writel(0, reg);
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/* Clear the falling-edge detect register */
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reg = gpio_reg(&priv->chip, base, GFER);
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writel(0, reg);
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/* Clear the edge detect status register */
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reg = gpio_reg(&priv->chip, base, GEDR);
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writel(~0, reg);
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}
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}
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static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct intel_mid_gpio *priv = d->host_data;
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irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq);
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irq_set_chip_data(irq, priv);
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irq_set_irq_type(irq, IRQ_TYPE_NONE);
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return 0;
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}
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static const struct irq_domain_ops intel_gpio_irq_ops = {
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.map = intel_gpio_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static int intel_gpio_runtime_idle(struct device *dev)
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{
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int err = pm_schedule_suspend(dev, 500);
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return err ?: -EBUSY;
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}
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static const struct dev_pm_ops intel_gpio_pm_ops = {
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SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
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};
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static int intel_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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void __iomem *base;
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struct intel_mid_gpio *priv;
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u32 gpio_base;
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u32 irq_base;
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int retval;
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struct intel_mid_gpio_ddata *ddata =
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(struct intel_mid_gpio_ddata *)id->driver_data;
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retval = pcim_enable_device(pdev);
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if (retval)
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return retval;
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retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
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if (retval) {
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dev_err(&pdev->dev, "I/O memory mapping error\n");
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return retval;
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}
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base = pcim_iomap_table(pdev)[1];
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irq_base = readl(base);
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gpio_base = readl(sizeof(u32) + base);
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/* release the IO mapping, since we already get the info from bar1 */
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pcim_iounmap_regions(pdev, 1 << 1);
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(&pdev->dev, "can't allocate chip data\n");
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return -ENOMEM;
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}
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priv->reg_base = pcim_iomap_table(pdev)[0];
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priv->chip.label = dev_name(&pdev->dev);
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priv->chip.dev = &pdev->dev;
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priv->chip.request = intel_gpio_request;
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priv->chip.direction_input = intel_gpio_direction_input;
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priv->chip.direction_output = intel_gpio_direction_output;
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priv->chip.get = intel_gpio_get;
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priv->chip.set = intel_gpio_set;
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priv->chip.to_irq = intel_gpio_to_irq;
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priv->chip.base = gpio_base;
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priv->chip.ngpio = ddata->ngpio;
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priv->chip.can_sleep = false;
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priv->pdev = pdev;
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spin_lock_init(&priv->lock);
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priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
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irq_base, &intel_gpio_irq_ops, priv);
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if (!priv->domain)
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return -ENOMEM;
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pci_set_drvdata(pdev, priv);
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retval = gpiochip_add(&priv->chip);
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if (retval) {
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dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
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return retval;
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}
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intel_mid_irq_init_hw(priv);
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irq_set_handler_data(pdev->irq, priv);
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irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);
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pm_runtime_put_noidle(&pdev->dev);
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pm_runtime_allow(&pdev->dev);
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return 0;
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}
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static struct pci_driver intel_gpio_driver = {
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.name = "intel_mid_gpio",
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.id_table = intel_gpio_ids,
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.probe = intel_gpio_probe,
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.driver = {
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.pm = &intel_gpio_pm_ops,
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},
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};
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static int __init intel_gpio_init(void)
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{
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return pci_register_driver(&intel_gpio_driver);
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}
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device_initcall(intel_gpio_init);
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