403 lines
10 KiB
C
403 lines
10 KiB
C
#include <linux/linkage.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/random.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/syscore_ops.h>
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#include <linux/bitops.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/atomic.h>
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#include <asm/system.h>
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#include <asm/timer.h>
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#include <asm/hw_irq.h>
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#include <asm/pgtable.h>
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#include <asm/desc.h>
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#include <asm/apic.h>
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#include <asm/i8259.h>
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/*
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* This is the 'legacy' 8259A Programmable Interrupt Controller,
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* present in the majority of PC/AT boxes.
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* plus some generic x86 specific things if generic specifics makes
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* any sense at all.
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*/
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static void init_8259A(int auto_eoi);
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static int i8259A_auto_eoi;
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DEFINE_RAW_SPINLOCK(i8259A_lock);
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/*
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* 8259A PIC functions to handle ISA devices:
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*/
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/*
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* This contains the irq mask for both 8259A irq controllers,
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*/
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unsigned int cached_irq_mask = 0xffff;
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/*
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* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
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* boards the timer interrupt is not really connected to any IO-APIC pin,
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* it's fed to the master 8259A's IR0 line only.
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*
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* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
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* this 'mixed mode' IRQ handling costs nothing because it's only used
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* at IRQ setup time.
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*/
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unsigned long io_apic_irqs;
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static void mask_8259A_irq(unsigned int irq)
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{
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unsigned int mask = 1 << irq;
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unsigned long flags;
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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cached_irq_mask |= mask;
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if (irq & 8)
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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else
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outb(cached_master_mask, PIC_MASTER_IMR);
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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static void disable_8259A_irq(struct irq_data *data)
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{
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mask_8259A_irq(data->irq);
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}
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static void unmask_8259A_irq(unsigned int irq)
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{
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unsigned int mask = ~(1 << irq);
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unsigned long flags;
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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cached_irq_mask &= mask;
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if (irq & 8)
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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else
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outb(cached_master_mask, PIC_MASTER_IMR);
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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static void enable_8259A_irq(struct irq_data *data)
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{
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unmask_8259A_irq(data->irq);
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}
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static int i8259A_irq_pending(unsigned int irq)
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{
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unsigned int mask = 1<<irq;
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unsigned long flags;
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int ret;
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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if (irq < 8)
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ret = inb(PIC_MASTER_CMD) & mask;
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else
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ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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return ret;
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}
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static void make_8259A_irq(unsigned int irq)
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{
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disable_irq_nosync(irq);
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io_apic_irqs &= ~(1<<irq);
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irq_set_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
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i8259A_chip.name);
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enable_irq(irq);
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}
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/*
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* This function assumes to be called rarely. Switching between
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* 8259A registers is slow.
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* This has to be protected by the irq controller spinlock
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* before being called.
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*/
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static inline int i8259A_irq_real(unsigned int irq)
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{
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int value;
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int irqmask = 1<<irq;
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if (irq < 8) {
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outb(0x0B, PIC_MASTER_CMD); /* ISR register */
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value = inb(PIC_MASTER_CMD) & irqmask;
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outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
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return value;
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}
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outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
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value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
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outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
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return value;
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}
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/*
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* Careful! The 8259A is a fragile beast, it pretty
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* much _has_ to be done exactly like this (mask it
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* first, _then_ send the EOI, and the order of EOI
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* to the two 8259s is important!
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*/
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static void mask_and_ack_8259A(struct irq_data *data)
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{
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unsigned int irq = data->irq;
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unsigned int irqmask = 1 << irq;
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unsigned long flags;
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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/*
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* Lightweight spurious IRQ detection. We do not want
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* to overdo spurious IRQ handling - it's usually a sign
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* of hardware problems, so we only do the checks we can
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* do without slowing down good hardware unnecessarily.
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*
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* Note that IRQ7 and IRQ15 (the two spurious IRQs
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* usually resulting from the 8259A-1|2 PICs) occur
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* even if the IRQ is masked in the 8259A. Thus we
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* can check spurious 8259A IRQs without doing the
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* quite slow i8259A_irq_real() call for every IRQ.
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* This does not cover 100% of spurious interrupts,
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* but should be enough to warn the user that there
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* is something bad going on ...
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*/
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if (cached_irq_mask & irqmask)
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goto spurious_8259A_irq;
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cached_irq_mask |= irqmask;
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handle_real_irq:
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if (irq & 8) {
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inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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/* 'Specific EOI' to slave */
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outb(0x60+(irq&7), PIC_SLAVE_CMD);
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/* 'Specific EOI' to master-IRQ2 */
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outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
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} else {
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inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
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outb(cached_master_mask, PIC_MASTER_IMR);
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outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
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}
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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return;
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spurious_8259A_irq:
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/*
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* this is the slow path - should happen rarely.
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*/
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if (i8259A_irq_real(irq))
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/*
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* oops, the IRQ _is_ in service according to the
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* 8259A - not spurious, go handle it.
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*/
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goto handle_real_irq;
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{
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static int spurious_irq_mask;
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/*
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* At this point we can be sure the IRQ is spurious,
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* lets ACK and report it. [once per IRQ]
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*/
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if (!(spurious_irq_mask & irqmask)) {
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printk(KERN_DEBUG
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"spurious 8259A interrupt: IRQ%d.\n", irq);
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spurious_irq_mask |= irqmask;
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}
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atomic_inc(&irq_err_count);
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/*
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* Theoretically we do not have to handle this IRQ,
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* but in Linux this does not cause problems and is
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* simpler for us.
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*/
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goto handle_real_irq;
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}
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}
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struct irq_chip i8259A_chip = {
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.name = "XT-PIC",
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.irq_mask = disable_8259A_irq,
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.irq_disable = disable_8259A_irq,
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.irq_unmask = enable_8259A_irq,
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.irq_mask_ack = mask_and_ack_8259A,
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};
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static char irq_trigger[2];
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/**
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* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
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*/
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static void restore_ELCR(char *trigger)
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{
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outb(trigger[0], 0x4d0);
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outb(trigger[1], 0x4d1);
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}
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static void save_ELCR(char *trigger)
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{
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/* IRQ 0,1,2,8,13 are marked as reserved */
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trigger[0] = inb(0x4d0) & 0xF8;
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trigger[1] = inb(0x4d1) & 0xDE;
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}
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static void i8259A_resume(void)
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{
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init_8259A(i8259A_auto_eoi);
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restore_ELCR(irq_trigger);
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}
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static int i8259A_suspend(void)
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{
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save_ELCR(irq_trigger);
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return 0;
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}
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static void i8259A_shutdown(void)
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{
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/* Put the i8259A into a quiescent state that
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* the kernel initialization code can get it
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* out of.
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*/
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outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
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outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
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}
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static struct syscore_ops i8259_syscore_ops = {
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.suspend = i8259A_suspend,
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.resume = i8259A_resume,
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.shutdown = i8259A_shutdown,
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};
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static void mask_8259A(void)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
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outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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static void unmask_8259A(void)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
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outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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static void init_8259A(int auto_eoi)
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{
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unsigned long flags;
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i8259A_auto_eoi = auto_eoi;
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
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outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
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/*
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* outb_pic - this has to work on a wide range of PC hardware.
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*/
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outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
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/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
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to 0x20-0x27 on i386 */
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outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
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/* 8259A-1 (the master) has a slave on IR2 */
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outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
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if (auto_eoi) /* master does Auto EOI */
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outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
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else /* master expects normal EOI */
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outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
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outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
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/* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
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outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
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/* 8259A-2 is a slave on master's IR2 */
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outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
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/* (slave's support for AEOI in flat mode is to be investigated) */
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outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
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if (auto_eoi)
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/*
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* In AEOI mode we just have to mask the interrupt
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* when acking.
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*/
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i8259A_chip.irq_mask_ack = disable_8259A_irq;
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else
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i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
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udelay(100); /* wait for 8259A to initialize */
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outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
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outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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/*
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* make i8259 a driver so that we can select pic functions at run time. the goal
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* is to make x86 binary compatible among pc compatible and non-pc compatible
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* platforms, such as x86 MID.
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*/
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static void legacy_pic_noop(void) { };
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static void legacy_pic_uint_noop(unsigned int unused) { };
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static void legacy_pic_int_noop(int unused) { };
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static int legacy_pic_irq_pending_noop(unsigned int irq)
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{
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return 0;
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}
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struct legacy_pic null_legacy_pic = {
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.nr_legacy_irqs = 0,
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.chip = &dummy_irq_chip,
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.mask = legacy_pic_uint_noop,
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.unmask = legacy_pic_uint_noop,
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.mask_all = legacy_pic_noop,
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.restore_mask = legacy_pic_noop,
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.init = legacy_pic_int_noop,
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.irq_pending = legacy_pic_irq_pending_noop,
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.make_irq = legacy_pic_uint_noop,
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};
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struct legacy_pic default_legacy_pic = {
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.nr_legacy_irqs = NR_IRQS_LEGACY,
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.chip = &i8259A_chip,
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.mask = mask_8259A_irq,
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.unmask = unmask_8259A_irq,
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.mask_all = mask_8259A,
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.restore_mask = unmask_8259A,
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.init = init_8259A,
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.irq_pending = i8259A_irq_pending,
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.make_irq = make_8259A_irq,
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};
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struct legacy_pic *legacy_pic = &default_legacy_pic;
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static int __init i8259A_init_ops(void)
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{
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if (legacy_pic == &default_legacy_pic)
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register_syscore_ops(&i8259_syscore_ops);
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return 0;
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}
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device_initcall(i8259A_init_ops);
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