86 lines
3.1 KiB
C
86 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* UFS PHY driver data for Samsung EXYNOS7 SoC
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*
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* Copyright (C) 2020 Samsung Electronics Co., Ltd.
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*/
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#include "phy-samsung-ufs.h"
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#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
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#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
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#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
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#define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
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/* Calibration for phy initialization */
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static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
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PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
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END_UFS_PHY_CFG
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};
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/* Calibration for HS mode series A/B */
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static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
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PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
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PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
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PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
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/* Setting order: 1st(0x16, 2nd(0x15) */
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PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
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PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
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PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
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PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
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PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
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PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
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PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
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PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
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PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
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PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
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PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
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PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
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PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
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PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
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END_UFS_PHY_CFG
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};
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/* Calibration for HS mode series A/B atfer PMC */
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static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
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PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
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PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
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END_UFS_PHY_CFG
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};
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static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
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[CFG_PRE_INIT] = exynos7_pre_init_cfg,
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[CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg,
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[CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
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};
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static const char * const exynos7_ufs_phy_clks[] = {
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"tx0_symbol_clk", "rx0_symbol_clk", "rx1_symbol_clk", "ref_clk",
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};
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const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
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.cfgs = exynos7_ufs_phy_cfgs,
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.isol = {
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.offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
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.mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
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.en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
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},
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.clk_list = exynos7_ufs_phy_clks,
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.num_clks = ARRAY_SIZE(exynos7_ufs_phy_clks),
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.cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
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};
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