40f05e5b0d
This patch fixes an inconsistency between code and spec, which was found while working on the QoS implementation. When 8TCs are used, 2 is the maximum supported number of index bits. In a 4TC mode, we do support 3, but we shouldn't really use the bytes, which are intended for the 8TC mode. Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| hw_atl_a0.c | ||
| hw_atl_a0.h | ||
| hw_atl_a0_internal.h | ||
| hw_atl_b0.c | ||
| hw_atl_b0.h | ||
| hw_atl_b0_internal.h | ||
| hw_atl_llh.c | ||
| hw_atl_llh.h | ||
| hw_atl_llh_internal.h | ||
| hw_atl_utils.c | ||
| hw_atl_utils.h | ||
| hw_atl_utils_fw2x.c | ||