115 lines
5.0 KiB
C
115 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#define FDOMAIN_REGION_SIZE 0x10
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#define FDOMAIN_BIOS_SIZE 0x2000
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enum {
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in_arbitration = 0x02,
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in_selection = 0x04,
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in_other = 0x08,
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disconnect = 0x10,
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aborted = 0x20,
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sent_ident = 0x40,
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};
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/* (@) = not present on TMC1800, (#) = not present on TMC1800 and TMC18C50 */
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#define REG_SCSI_DATA 0 /* R/W: SCSI Data (with ACK) */
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#define REG_BSTAT 1 /* R: SCSI Bus Status */
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#define BSTAT_BSY BIT(0) /* Busy */
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#define BSTAT_MSG BIT(1) /* Message */
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#define BSTAT_IO BIT(2) /* Input/Output */
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#define BSTAT_CMD BIT(3) /* Command/Data */
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#define BSTAT_REQ BIT(4) /* Request and Not Ack */
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#define BSTAT_SEL BIT(5) /* Select */
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#define BSTAT_ACK BIT(6) /* Acknowledge and Request */
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#define BSTAT_ATN BIT(7) /* Attention */
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#define REG_BCTL 1 /* W: SCSI Bus Control */
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#define BCTL_RST BIT(0) /* Bus Reset */
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#define BCTL_SEL BIT(1) /* Select */
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#define BCTL_BSY BIT(2) /* Busy */
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#define BCTL_ATN BIT(3) /* Attention */
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#define BCTL_IO BIT(4) /* Input/Output */
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#define BCTL_CMD BIT(5) /* Command/Data */
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#define BCTL_MSG BIT(6) /* Message */
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#define BCTL_BUSEN BIT(7) /* Enable bus drivers */
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#define REG_ASTAT 2 /* R: Adapter Status 1 */
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#define ASTAT_IRQ BIT(0) /* Interrupt active */
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#define ASTAT_ARB BIT(1) /* Arbitration complete */
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#define ASTAT_PARERR BIT(2) /* Parity error */
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#define ASTAT_RST BIT(3) /* SCSI reset occurred */
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#define ASTAT_FIFODIR BIT(4) /* FIFO direction */
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#define ASTAT_FIFOEN BIT(5) /* FIFO enabled */
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#define ASTAT_PAREN BIT(6) /* Parity enabled */
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#define ASTAT_BUSEN BIT(7) /* Bus drivers enabled */
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#define REG_ICTL 2 /* W: Interrupt Control */
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#define ICTL_FIFO_MASK 0x0f /* FIFO threshold, 1/16 FIFO size */
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#define ICTL_FIFO BIT(4) /* Int. on FIFO count */
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#define ICTL_ARB BIT(5) /* Int. on Arbitration complete */
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#define ICTL_SEL BIT(6) /* Int. on SCSI Select */
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#define ICTL_REQ BIT(7) /* Int. on SCSI Request */
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#define REG_FSTAT 3 /* R: Adapter Status 2 (FIFO) - (@) */
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#define FSTAT_ONOTEMPTY BIT(0) /* Output FIFO not empty */
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#define FSTAT_INOTEMPTY BIT(1) /* Input FIFO not empty */
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#define FSTAT_NOTEMPTY BIT(2) /* Main FIFO not empty */
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#define FSTAT_NOTFULL BIT(3) /* Main FIFO not full */
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#define REG_MCTL 3 /* W: SCSI Data Mode Control */
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#define MCTL_ACK_MASK 0x0f /* Acknowledge period */
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#define MCTL_ACTDEASS BIT(4) /* Active deassert of REQ and ACK */
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#define MCTL_TARGET BIT(5) /* Enable target mode */
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#define MCTL_FASTSYNC BIT(6) /* Enable Fast Synchronous */
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#define MCTL_SYNC BIT(7) /* Enable Synchronous */
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#define REG_INTCOND 4 /* R: Interrupt Condition - (@) */
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#define IRQ_FIFO BIT(1) /* FIFO interrupt */
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#define IRQ_REQ BIT(2) /* SCSI Request interrupt */
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#define IRQ_SEL BIT(3) /* SCSI Select interrupt */
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#define IRQ_ARB BIT(4) /* SCSI Arbitration interrupt */
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#define IRQ_RST BIT(5) /* SCSI Reset interrupt */
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#define IRQ_FORCED BIT(6) /* Forced interrupt */
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#define IRQ_TIMEOUT BIT(7) /* Bus timeout */
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#define REG_ACTL 4 /* W: Adapter Control 1 */
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#define ACTL_RESET BIT(0) /* Reset FIFO, parity, reset int. */
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#define ACTL_FIRQ BIT(1) /* Set Forced interrupt */
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#define ACTL_ARB BIT(2) /* Initiate Bus Arbitration */
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#define ACTL_PAREN BIT(3) /* Enable SCSI Parity */
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#define ACTL_IRQEN BIT(4) /* Enable interrupts */
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#define ACTL_CLRFIRQ BIT(5) /* Clear Forced interrupt */
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#define ACTL_FIFOWR BIT(6) /* FIFO Direction (1=write) */
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#define ACTL_FIFOEN BIT(7) /* Enable FIFO */
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#define REG_ID_LSB 5 /* R: ID Code (LSB) */
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#define REG_ACTL2 5 /* Adapter Control 2 - (@) */
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#define ACTL2_RAMOVRLY BIT(0) /* Enable RAM overlay */
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#define ACTL2_SLEEP BIT(7) /* Sleep mode */
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#define REG_ID_MSB 6 /* R: ID Code (MSB) */
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#define REG_LOOPBACK 7 /* R/W: Loopback */
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#define REG_SCSI_DATA_NOACK 8 /* R/W: SCSI Data (no ACK) */
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#define REG_ASTAT3 9 /* R: Adapter Status 3 */
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#define ASTAT3_ACTDEASS BIT(0) /* Active deassert enabled */
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#define ASTAT3_RAMOVRLY BIT(1) /* RAM overlay enabled */
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#define ASTAT3_TARGERR BIT(2) /* Target error */
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#define ASTAT3_IRQEN BIT(3) /* Interrupts enabled */
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#define ASTAT3_IRQMASK 0xf0 /* Enabled interrupts mask */
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#define REG_CFG1 10 /* R: Configuration Register 1 */
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#define CFG1_BUS BIT(0) /* 0 = ISA */
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#define CFG1_IRQ_MASK 0x0e /* IRQ jumpers */
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#define CFG1_IO_MASK 0x30 /* I/O base jumpers */
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#define CFG1_BIOS_MASK 0xc0 /* BIOS base jumpers */
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#define REG_CFG2 11 /* R/W: Configuration Register 2 (@) */
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#define CFG2_ROMDIS BIT(0) /* ROM disabled */
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#define CFG2_RAMDIS BIT(1) /* RAM disabled */
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#define CFG2_IRQEDGE BIT(2) /* Edge-triggered interrupts */
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#define CFG2_NOWS BIT(3) /* No wait states */
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#define CFG2_32BIT BIT(7) /* 32-bit mode */
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#define REG_FIFO 12 /* R/W: FIFO */
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#define REG_FIFO_COUNT 14 /* R: FIFO Data Count */
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#ifdef CONFIG_PM_SLEEP
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static const struct dev_pm_ops fdomain_pm_ops;
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#define FDOMAIN_PM_OPS (&fdomain_pm_ops)
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#else
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#define FDOMAIN_PM_OPS NULL
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#endif /* CONFIG_PM_SLEEP */
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struct Scsi_Host *fdomain_create(int base, int irq, int this_id,
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struct device *dev);
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int fdomain_destroy(struct Scsi_Host *sh);
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