376 lines
11 KiB
C
376 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Kernel-based Virtual Machine driver for Linux
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*
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* Macros and functions to access KVM PTEs (also known as SPTEs)
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*
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* Copyright (C) 2006 Qumranet, Inc.
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* Copyright 2020 Red Hat, Inc. and/or its affiliates.
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*/
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#include <linux/kvm_host.h>
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#include "mmu.h"
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#include "mmu_internal.h"
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#include "x86.h"
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#include "spte.h"
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#include <asm/e820/api.h>
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#include <asm/vmx.h>
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static bool __read_mostly enable_mmio_caching = true;
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module_param_named(mmio_caching, enable_mmio_caching, bool, 0444);
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u64 __read_mostly shadow_host_writable_mask;
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u64 __read_mostly shadow_mmu_writable_mask;
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u64 __read_mostly shadow_nx_mask;
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u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
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u64 __read_mostly shadow_user_mask;
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u64 __read_mostly shadow_accessed_mask;
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u64 __read_mostly shadow_dirty_mask;
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u64 __read_mostly shadow_mmio_value;
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u64 __read_mostly shadow_mmio_mask;
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u64 __read_mostly shadow_mmio_access_mask;
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u64 __read_mostly shadow_present_mask;
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u64 __read_mostly shadow_me_mask;
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u64 __read_mostly shadow_acc_track_mask;
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u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
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u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
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u8 __read_mostly shadow_phys_bits;
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static u64 generation_mmio_spte_mask(u64 gen)
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{
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u64 mask;
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WARN_ON(gen & ~MMIO_SPTE_GEN_MASK);
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mask = (gen << MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_SPTE_GEN_LOW_MASK;
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mask |= (gen << MMIO_SPTE_GEN_HIGH_SHIFT) & MMIO_SPTE_GEN_HIGH_MASK;
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return mask;
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}
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u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access)
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{
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u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;
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u64 spte = generation_mmio_spte_mask(gen);
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u64 gpa = gfn << PAGE_SHIFT;
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WARN_ON_ONCE(!shadow_mmio_value);
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access &= shadow_mmio_access_mask;
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spte |= shadow_mmio_value | access;
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spte |= gpa | shadow_nonpresent_or_rsvd_mask;
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spte |= (gpa & shadow_nonpresent_or_rsvd_mask)
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<< SHADOW_NONPRESENT_OR_RSVD_MASK_LEN;
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return spte;
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}
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static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
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{
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if (pfn_valid(pfn))
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return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) &&
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/*
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* Some reserved pages, such as those from NVDIMM
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* DAX devices, are not for MMIO, and can be mapped
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* with cached memory type for better performance.
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* However, the above check misconceives those pages
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* as MMIO, and results in KVM mapping them with UC
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* memory type, which would hurt the performance.
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* Therefore, we check the host memory type in addition
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* and only treat UC/UC-/WC pages as MMIO.
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*/
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(!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn));
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return !e820__mapped_raw_any(pfn_to_hpa(pfn),
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pfn_to_hpa(pfn + 1) - 1,
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E820_TYPE_RAM);
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}
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int make_spte(struct kvm_vcpu *vcpu, unsigned int pte_access, int level,
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gfn_t gfn, kvm_pfn_t pfn, u64 old_spte, bool speculative,
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bool can_unsync, bool host_writable, bool ad_disabled,
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u64 *new_spte)
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{
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u64 spte = SPTE_MMU_PRESENT_MASK;
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int ret = 0;
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if (ad_disabled)
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spte |= SPTE_TDP_AD_DISABLED_MASK;
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else if (kvm_vcpu_ad_need_write_protect(vcpu))
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spte |= SPTE_TDP_AD_WRPROT_ONLY_MASK;
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/*
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* Bits 62:52 of PAE SPTEs are reserved. WARN if said bits are set
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* if PAE paging may be employed (shadow paging or any 32-bit KVM).
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*/
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WARN_ON_ONCE((!tdp_enabled || !IS_ENABLED(CONFIG_X86_64)) &&
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(spte & SPTE_TDP_AD_MASK));
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/*
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* For the EPT case, shadow_present_mask is 0 if hardware
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* supports exec-only page table entries. In that case,
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* ACC_USER_MASK and shadow_user_mask are used to represent
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* read access. See FNAME(gpte_access) in paging_tmpl.h.
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*/
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spte |= shadow_present_mask;
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if (!speculative)
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spte |= spte_shadow_accessed_mask(spte);
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if (level > PG_LEVEL_4K && (pte_access & ACC_EXEC_MASK) &&
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is_nx_huge_page_enabled()) {
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pte_access &= ~ACC_EXEC_MASK;
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}
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if (pte_access & ACC_EXEC_MASK)
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spte |= shadow_x_mask;
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else
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spte |= shadow_nx_mask;
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if (pte_access & ACC_USER_MASK)
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spte |= shadow_user_mask;
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if (level > PG_LEVEL_4K)
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spte |= PT_PAGE_SIZE_MASK;
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if (tdp_enabled)
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spte |= static_call(kvm_x86_get_mt_mask)(vcpu, gfn,
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kvm_is_mmio_pfn(pfn));
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if (host_writable)
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spte |= shadow_host_writable_mask;
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else
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pte_access &= ~ACC_WRITE_MASK;
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if (!kvm_is_mmio_pfn(pfn))
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spte |= shadow_me_mask;
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spte |= (u64)pfn << PAGE_SHIFT;
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if (pte_access & ACC_WRITE_MASK) {
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spte |= PT_WRITABLE_MASK | shadow_mmu_writable_mask;
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/*
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* Optimization: for pte sync, if spte was writable the hash
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* lookup is unnecessary (and expensive). Write protection
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* is responsibility of mmu_get_page / kvm_sync_page.
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* Same reasoning can be applied to dirty page accounting.
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*/
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if (!can_unsync && is_writable_pte(old_spte))
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goto out;
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if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
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pgprintk("%s: found shadow page for %llx, marking ro\n",
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__func__, gfn);
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ret |= SET_SPTE_WRITE_PROTECTED_PT;
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pte_access &= ~ACC_WRITE_MASK;
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spte &= ~(PT_WRITABLE_MASK | shadow_mmu_writable_mask);
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}
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}
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if (pte_access & ACC_WRITE_MASK)
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spte |= spte_shadow_dirty_mask(spte);
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if (speculative)
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spte = mark_spte_for_access_track(spte);
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out:
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WARN_ON(is_mmio_spte(spte));
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*new_spte = spte;
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return ret;
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}
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u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled)
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{
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u64 spte = SPTE_MMU_PRESENT_MASK;
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spte |= __pa(child_pt) | shadow_present_mask | PT_WRITABLE_MASK |
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shadow_user_mask | shadow_x_mask | shadow_me_mask;
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if (ad_disabled)
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spte |= SPTE_TDP_AD_DISABLED_MASK;
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else
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spte |= shadow_accessed_mask;
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return spte;
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}
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u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn)
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{
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u64 new_spte;
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new_spte = old_spte & ~PT64_BASE_ADDR_MASK;
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new_spte |= (u64)new_pfn << PAGE_SHIFT;
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new_spte &= ~PT_WRITABLE_MASK;
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new_spte &= ~shadow_host_writable_mask;
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new_spte = mark_spte_for_access_track(new_spte);
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return new_spte;
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}
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static u8 kvm_get_shadow_phys_bits(void)
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{
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/*
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* boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
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* in CPU detection code, but the processor treats those reduced bits as
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* 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
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* the physical address bits reported by CPUID.
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*/
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if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008))
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return cpuid_eax(0x80000008) & 0xff;
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/*
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* Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
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* custom CPUID. Proceed with whatever the kernel found since these features
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* aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
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*/
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return boot_cpu_data.x86_phys_bits;
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}
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u64 mark_spte_for_access_track(u64 spte)
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{
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if (spte_ad_enabled(spte))
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return spte & ~shadow_accessed_mask;
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if (is_access_track_spte(spte))
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return spte;
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/*
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* Making an Access Tracking PTE will result in removal of write access
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* from the PTE. So, verify that we will be able to restore the write
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* access in the fast page fault path later on.
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*/
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WARN_ONCE((spte & PT_WRITABLE_MASK) &&
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!spte_can_locklessly_be_made_writable(spte),
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"kvm: Writable SPTE is not locklessly dirty-trackable\n");
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WARN_ONCE(spte & (SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
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SHADOW_ACC_TRACK_SAVED_BITS_SHIFT),
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"kvm: Access Tracking saved bit locations are not zero\n");
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spte |= (spte & SHADOW_ACC_TRACK_SAVED_BITS_MASK) <<
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SHADOW_ACC_TRACK_SAVED_BITS_SHIFT;
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spte &= ~shadow_acc_track_mask;
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return spte;
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}
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void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask)
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{
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BUG_ON((u64)(unsigned)access_mask != access_mask);
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WARN_ON(mmio_value & shadow_nonpresent_or_rsvd_lower_gfn_mask);
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if (!enable_mmio_caching)
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mmio_value = 0;
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/*
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* Disable MMIO caching if the MMIO value collides with the bits that
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* are used to hold the relocated GFN when the L1TF mitigation is
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* enabled. This should never fire as there is no known hardware that
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* can trigger this condition, e.g. SME/SEV CPUs that require a custom
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* MMIO value are not susceptible to L1TF.
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*/
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if (WARN_ON(mmio_value & (shadow_nonpresent_or_rsvd_mask <<
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SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)))
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mmio_value = 0;
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/*
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* The masked MMIO value must obviously match itself and a removed SPTE
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* must not get a false positive. Removed SPTEs and MMIO SPTEs should
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* never collide as MMIO must set some RWX bits, and removed SPTEs must
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* not set any RWX bits.
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*/
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if (WARN_ON((mmio_value & mmio_mask) != mmio_value) ||
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WARN_ON(mmio_value && (REMOVED_SPTE & mmio_mask) == mmio_value))
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mmio_value = 0;
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shadow_mmio_value = mmio_value;
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shadow_mmio_mask = mmio_mask;
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shadow_mmio_access_mask = access_mask;
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
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void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only)
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{
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shadow_user_mask = VMX_EPT_READABLE_MASK;
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shadow_accessed_mask = has_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull;
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shadow_dirty_mask = has_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull;
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shadow_nx_mask = 0ull;
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shadow_x_mask = VMX_EPT_EXECUTABLE_MASK;
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shadow_present_mask = has_exec_only ? 0ull : VMX_EPT_READABLE_MASK;
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shadow_acc_track_mask = VMX_EPT_RWX_MASK;
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shadow_me_mask = 0ull;
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shadow_host_writable_mask = EPT_SPTE_HOST_WRITABLE;
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shadow_mmu_writable_mask = EPT_SPTE_MMU_WRITABLE;
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/*
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* EPT Misconfigurations are generated if the value of bits 2:0
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* of an EPT paging-structure entry is 110b (write/execute).
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*/
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kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE,
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VMX_EPT_RWX_MASK, 0);
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_set_ept_masks);
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void kvm_mmu_reset_all_pte_masks(void)
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{
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u8 low_phys_bits;
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u64 mask;
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shadow_phys_bits = kvm_get_shadow_phys_bits();
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/*
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* If the CPU has 46 or less physical address bits, then set an
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* appropriate mask to guard against L1TF attacks. Otherwise, it is
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* assumed that the CPU is not vulnerable to L1TF.
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*
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* Some Intel CPUs address the L1 cache using more PA bits than are
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* reported by CPUID. Use the PA width of the L1 cache when possible
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* to achieve more effective mitigation, e.g. if system RAM overlaps
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* the most significant bits of legal physical address space.
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*/
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shadow_nonpresent_or_rsvd_mask = 0;
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low_phys_bits = boot_cpu_data.x86_phys_bits;
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if (boot_cpu_has_bug(X86_BUG_L1TF) &&
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!WARN_ON_ONCE(boot_cpu_data.x86_cache_bits >=
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52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) {
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low_phys_bits = boot_cpu_data.x86_cache_bits
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- SHADOW_NONPRESENT_OR_RSVD_MASK_LEN;
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shadow_nonpresent_or_rsvd_mask =
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rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1);
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}
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shadow_nonpresent_or_rsvd_lower_gfn_mask =
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GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
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shadow_user_mask = PT_USER_MASK;
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shadow_accessed_mask = PT_ACCESSED_MASK;
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shadow_dirty_mask = PT_DIRTY_MASK;
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shadow_nx_mask = PT64_NX_MASK;
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shadow_x_mask = 0;
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shadow_present_mask = PT_PRESENT_MASK;
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shadow_acc_track_mask = 0;
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shadow_me_mask = sme_me_mask;
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shadow_host_writable_mask = DEFAULT_SPTE_HOST_WRITEABLE;
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shadow_mmu_writable_mask = DEFAULT_SPTE_MMU_WRITEABLE;
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/*
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* Set a reserved PA bit in MMIO SPTEs to generate page faults with
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* PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
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* paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
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* 52-bit physical addresses then there are no reserved PA bits in the
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* PTEs and so the reserved PA approach must be disabled.
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*/
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if (shadow_phys_bits < 52)
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mask = BIT_ULL(51) | PT_PRESENT_MASK;
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else
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mask = 0;
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kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK);
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}
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