736 lines
17 KiB
C
736 lines
17 KiB
C
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/iommu.h>
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#include <linux/clk.h>
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#include <asm/cacheflush.h>
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#include <asm/sizes.h>
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#include "msm_iommu_hw-8xxx.h"
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#include "msm_iommu.h"
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#define MRC(reg, processor, op1, crn, crm, op2) \
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__asm__ __volatile__ ( \
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" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
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: "=r" (reg))
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#define RCP15_PRRR(reg) MRC(reg, p15, 0, c10, c2, 0)
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#define RCP15_NMRR(reg) MRC(reg, p15, 0, c10, c2, 1)
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/* bitmap of the page sizes currently supported */
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#define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
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static int msm_iommu_tex_class[4];
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DEFINE_SPINLOCK(msm_iommu_lock);
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struct msm_priv {
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unsigned long *pgtable;
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struct list_head list_attached;
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struct iommu_domain domain;
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};
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static struct msm_priv *to_msm_priv(struct iommu_domain *dom)
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{
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return container_of(dom, struct msm_priv, domain);
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}
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static int __enable_clocks(struct msm_iommu_drvdata *drvdata)
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{
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int ret;
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ret = clk_enable(drvdata->pclk);
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if (ret)
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goto fail;
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if (drvdata->clk) {
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ret = clk_enable(drvdata->clk);
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if (ret)
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clk_disable(drvdata->pclk);
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}
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fail:
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return ret;
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}
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static void __disable_clocks(struct msm_iommu_drvdata *drvdata)
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{
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clk_disable(drvdata->clk);
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clk_disable(drvdata->pclk);
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}
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static int __flush_iotlb(struct iommu_domain *domain)
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{
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struct msm_priv *priv = to_msm_priv(domain);
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struct msm_iommu_drvdata *iommu_drvdata;
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struct msm_iommu_ctx_drvdata *ctx_drvdata;
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int ret = 0;
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#ifndef CONFIG_IOMMU_PGTABLES_L2
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unsigned long *fl_table = priv->pgtable;
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int i;
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if (!list_empty(&priv->list_attached)) {
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dmac_flush_range(fl_table, fl_table + SZ_16K);
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for (i = 0; i < NUM_FL_PTE; i++)
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if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
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void *sl_table = __va(fl_table[i] &
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FL_BASE_MASK);
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dmac_flush_range(sl_table, sl_table + SZ_4K);
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}
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}
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#endif
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list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
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BUG_ON(!ctx_drvdata->pdev || !ctx_drvdata->pdev->dev.parent);
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iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
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BUG_ON(!iommu_drvdata);
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ret = __enable_clocks(iommu_drvdata);
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if (ret)
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goto fail;
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SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
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__disable_clocks(iommu_drvdata);
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}
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fail:
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return ret;
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}
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static void __reset_context(void __iomem *base, int ctx)
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{
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SET_BPRCOSH(base, ctx, 0);
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SET_BPRCISH(base, ctx, 0);
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SET_BPRCNSH(base, ctx, 0);
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SET_BPSHCFG(base, ctx, 0);
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SET_BPMTCFG(base, ctx, 0);
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SET_ACTLR(base, ctx, 0);
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SET_SCTLR(base, ctx, 0);
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SET_FSRRESTORE(base, ctx, 0);
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SET_TTBR0(base, ctx, 0);
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SET_TTBR1(base, ctx, 0);
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SET_TTBCR(base, ctx, 0);
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SET_BFBCR(base, ctx, 0);
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SET_PAR(base, ctx, 0);
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SET_FAR(base, ctx, 0);
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SET_CTX_TLBIALL(base, ctx, 0);
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SET_TLBFLPTER(base, ctx, 0);
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SET_TLBSLPTER(base, ctx, 0);
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SET_TLBLKCR(base, ctx, 0);
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SET_PRRR(base, ctx, 0);
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SET_NMRR(base, ctx, 0);
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}
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static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
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{
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unsigned int prrr, nmrr;
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__reset_context(base, ctx);
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/* Set up HTW mode */
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/* TLB miss configuration: perform HTW on miss */
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SET_TLBMCFG(base, ctx, 0x3);
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/* V2P configuration: HTW for access */
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SET_V2PCFG(base, ctx, 0x3);
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SET_TTBCR(base, ctx, 0);
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SET_TTBR0_PA(base, ctx, (pgtable >> 14));
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/* Invalidate the TLB for this context */
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SET_CTX_TLBIALL(base, ctx, 0);
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/* Set interrupt number to "secure" interrupt */
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SET_IRPTNDX(base, ctx, 0);
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/* Enable context fault interrupt */
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SET_CFEIE(base, ctx, 1);
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/* Stall access on a context fault and let the handler deal with it */
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SET_CFCFG(base, ctx, 1);
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/* Redirect all cacheable requests to L2 slave port. */
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SET_RCISH(base, ctx, 1);
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SET_RCOSH(base, ctx, 1);
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SET_RCNSH(base, ctx, 1);
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/* Turn on TEX Remap */
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SET_TRE(base, ctx, 1);
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/* Set TEX remap attributes */
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RCP15_PRRR(prrr);
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RCP15_NMRR(nmrr);
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SET_PRRR(base, ctx, prrr);
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SET_NMRR(base, ctx, nmrr);
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/* Turn on BFB prefetch */
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SET_BFBDFE(base, ctx, 1);
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#ifdef CONFIG_IOMMU_PGTABLES_L2
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/* Configure page tables as inner-cacheable and shareable to reduce
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* the TLB miss penalty.
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*/
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SET_TTBR0_SH(base, ctx, 1);
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SET_TTBR1_SH(base, ctx, 1);
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SET_TTBR0_NOS(base, ctx, 1);
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SET_TTBR1_NOS(base, ctx, 1);
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SET_TTBR0_IRGNH(base, ctx, 0); /* WB, WA */
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SET_TTBR0_IRGNL(base, ctx, 1);
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SET_TTBR1_IRGNH(base, ctx, 0); /* WB, WA */
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SET_TTBR1_IRGNL(base, ctx, 1);
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SET_TTBR0_ORGN(base, ctx, 1); /* WB, WA */
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SET_TTBR1_ORGN(base, ctx, 1); /* WB, WA */
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#endif
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/* Enable the MMU */
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SET_M(base, ctx, 1);
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}
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static struct iommu_domain *msm_iommu_domain_alloc(unsigned type)
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{
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struct msm_priv *priv;
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if (type != IOMMU_DOMAIN_UNMANAGED)
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return NULL;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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goto fail_nomem;
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INIT_LIST_HEAD(&priv->list_attached);
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priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL,
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get_order(SZ_16K));
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if (!priv->pgtable)
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goto fail_nomem;
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memset(priv->pgtable, 0, SZ_16K);
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priv->domain.geometry.aperture_start = 0;
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priv->domain.geometry.aperture_end = (1ULL << 32) - 1;
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priv->domain.geometry.force_aperture = true;
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return &priv->domain;
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fail_nomem:
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kfree(priv);
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return NULL;
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}
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static void msm_iommu_domain_free(struct iommu_domain *domain)
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{
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struct msm_priv *priv;
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unsigned long flags;
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unsigned long *fl_table;
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int i;
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spin_lock_irqsave(&msm_iommu_lock, flags);
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priv = to_msm_priv(domain);
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fl_table = priv->pgtable;
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for (i = 0; i < NUM_FL_PTE; i++)
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if ((fl_table[i] & 0x03) == FL_TYPE_TABLE)
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free_page((unsigned long) __va(((fl_table[i]) &
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FL_BASE_MASK)));
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free_pages((unsigned long)priv->pgtable, get_order(SZ_16K));
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priv->pgtable = NULL;
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kfree(priv);
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spin_unlock_irqrestore(&msm_iommu_lock, flags);
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}
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static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
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{
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struct msm_priv *priv;
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struct msm_iommu_ctx_dev *ctx_dev;
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struct msm_iommu_drvdata *iommu_drvdata;
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struct msm_iommu_ctx_drvdata *ctx_drvdata;
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struct msm_iommu_ctx_drvdata *tmp_drvdata;
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&msm_iommu_lock, flags);
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priv = to_msm_priv(domain);
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if (!dev) {
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ret = -EINVAL;
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goto fail;
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}
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iommu_drvdata = dev_get_drvdata(dev->parent);
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ctx_drvdata = dev_get_drvdata(dev);
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ctx_dev = dev->platform_data;
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if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) {
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ret = -EINVAL;
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goto fail;
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}
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if (!list_empty(&ctx_drvdata->attached_elm)) {
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ret = -EBUSY;
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goto fail;
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}
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list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
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if (tmp_drvdata == ctx_drvdata) {
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ret = -EBUSY;
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goto fail;
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}
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ret = __enable_clocks(iommu_drvdata);
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if (ret)
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goto fail;
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__program_context(iommu_drvdata->base, ctx_dev->num,
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__pa(priv->pgtable));
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__disable_clocks(iommu_drvdata);
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list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
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ret = __flush_iotlb(domain);
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fail:
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spin_unlock_irqrestore(&msm_iommu_lock, flags);
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return ret;
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}
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static void msm_iommu_detach_dev(struct iommu_domain *domain,
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struct device *dev)
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{
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struct msm_priv *priv;
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struct msm_iommu_ctx_dev *ctx_dev;
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struct msm_iommu_drvdata *iommu_drvdata;
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struct msm_iommu_ctx_drvdata *ctx_drvdata;
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&msm_iommu_lock, flags);
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priv = to_msm_priv(domain);
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if (!dev)
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goto fail;
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iommu_drvdata = dev_get_drvdata(dev->parent);
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ctx_drvdata = dev_get_drvdata(dev);
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ctx_dev = dev->platform_data;
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if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
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goto fail;
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ret = __flush_iotlb(domain);
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if (ret)
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goto fail;
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ret = __enable_clocks(iommu_drvdata);
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if (ret)
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goto fail;
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__reset_context(iommu_drvdata->base, ctx_dev->num);
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__disable_clocks(iommu_drvdata);
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list_del_init(&ctx_drvdata->attached_elm);
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fail:
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spin_unlock_irqrestore(&msm_iommu_lock, flags);
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}
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static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
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phys_addr_t pa, size_t len, int prot)
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{
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struct msm_priv *priv;
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unsigned long flags;
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unsigned long *fl_table;
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unsigned long *fl_pte;
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unsigned long fl_offset;
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unsigned long *sl_table;
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unsigned long *sl_pte;
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unsigned long sl_offset;
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unsigned int pgprot;
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int ret = 0, tex, sh;
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spin_lock_irqsave(&msm_iommu_lock, flags);
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sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0;
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tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK];
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if (tex < 0 || tex > NUM_TEX_CLASS - 1) {
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ret = -EINVAL;
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goto fail;
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}
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priv = to_msm_priv(domain);
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fl_table = priv->pgtable;
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if (len != SZ_16M && len != SZ_1M &&
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len != SZ_64K && len != SZ_4K) {
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pr_debug("Bad size: %d\n", len);
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ret = -EINVAL;
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goto fail;
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}
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if (!fl_table) {
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pr_debug("Null page table\n");
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ret = -EINVAL;
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goto fail;
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}
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if (len == SZ_16M || len == SZ_1M) {
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pgprot = sh ? FL_SHARED : 0;
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pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0;
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pgprot |= tex & 0x02 ? FL_CACHEABLE : 0;
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pgprot |= tex & 0x04 ? FL_TEX0 : 0;
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} else {
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pgprot = sh ? SL_SHARED : 0;
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pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0;
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pgprot |= tex & 0x02 ? SL_CACHEABLE : 0;
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pgprot |= tex & 0x04 ? SL_TEX0 : 0;
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}
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fl_offset = FL_OFFSET(va); /* Upper 12 bits */
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fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
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if (len == SZ_16M) {
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int i = 0;
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for (i = 0; i < 16; i++)
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*(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
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FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
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FL_SHARED | FL_NG | pgprot;
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}
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if (len == SZ_1M)
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*fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | FL_NG |
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FL_TYPE_SECT | FL_SHARED | pgprot;
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/* Need a 2nd level table */
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if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
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unsigned long *sl;
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sl = (unsigned long *) __get_free_pages(GFP_ATOMIC,
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get_order(SZ_4K));
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if (!sl) {
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pr_debug("Could not allocate second level table\n");
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ret = -ENOMEM;
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goto fail;
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}
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memset(sl, 0, SZ_4K);
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*fl_pte = ((((int)__pa(sl)) & FL_BASE_MASK) | FL_TYPE_TABLE);
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}
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sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
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sl_offset = SL_OFFSET(va);
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sl_pte = sl_table + sl_offset;
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|
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if (len == SZ_4K)
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*sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | SL_NG |
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SL_SHARED | SL_TYPE_SMALL | pgprot;
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if (len == SZ_64K) {
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int i;
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for (i = 0; i < 16; i++)
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*(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
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SL_NG | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot;
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}
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ret = __flush_iotlb(domain);
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fail:
|
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spin_unlock_irqrestore(&msm_iommu_lock, flags);
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return ret;
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}
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|
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static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
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size_t len)
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{
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struct msm_priv *priv;
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unsigned long flags;
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unsigned long *fl_table;
|
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unsigned long *fl_pte;
|
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unsigned long fl_offset;
|
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unsigned long *sl_table;
|
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unsigned long *sl_pte;
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unsigned long sl_offset;
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int i, ret = 0;
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|
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spin_lock_irqsave(&msm_iommu_lock, flags);
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priv = to_msm_priv(domain);
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fl_table = priv->pgtable;
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|
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if (len != SZ_16M && len != SZ_1M &&
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len != SZ_64K && len != SZ_4K) {
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pr_debug("Bad length: %d\n", len);
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goto fail;
|
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}
|
|
|
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if (!fl_table) {
|
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pr_debug("Null page table\n");
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goto fail;
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}
|
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|
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fl_offset = FL_OFFSET(va); /* Upper 12 bits */
|
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fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
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|
|
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if (*fl_pte == 0) {
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pr_debug("First level PTE is 0\n");
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goto fail;
|
|
}
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|
|
|
/* Unmap supersection */
|
|
if (len == SZ_16M)
|
|
for (i = 0; i < 16; i++)
|
|
*(fl_pte+i) = 0;
|
|
|
|
if (len == SZ_1M)
|
|
*fl_pte = 0;
|
|
|
|
sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
|
|
sl_offset = SL_OFFSET(va);
|
|
sl_pte = sl_table + sl_offset;
|
|
|
|
if (len == SZ_64K) {
|
|
for (i = 0; i < 16; i++)
|
|
*(sl_pte+i) = 0;
|
|
}
|
|
|
|
if (len == SZ_4K)
|
|
*sl_pte = 0;
|
|
|
|
if (len == SZ_4K || len == SZ_64K) {
|
|
int used = 0;
|
|
|
|
for (i = 0; i < NUM_SL_PTE; i++)
|
|
if (sl_table[i])
|
|
used = 1;
|
|
if (!used) {
|
|
free_page((unsigned long)sl_table);
|
|
*fl_pte = 0;
|
|
}
|
|
}
|
|
|
|
ret = __flush_iotlb(domain);
|
|
|
|
fail:
|
|
spin_unlock_irqrestore(&msm_iommu_lock, flags);
|
|
|
|
/* the IOMMU API requires us to return how many bytes were unmapped */
|
|
len = ret ? 0 : len;
|
|
return len;
|
|
}
|
|
|
|
static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
|
|
dma_addr_t va)
|
|
{
|
|
struct msm_priv *priv;
|
|
struct msm_iommu_drvdata *iommu_drvdata;
|
|
struct msm_iommu_ctx_drvdata *ctx_drvdata;
|
|
unsigned int par;
|
|
unsigned long flags;
|
|
void __iomem *base;
|
|
phys_addr_t ret = 0;
|
|
int ctx;
|
|
|
|
spin_lock_irqsave(&msm_iommu_lock, flags);
|
|
|
|
priv = to_msm_priv(domain);
|
|
if (list_empty(&priv->list_attached))
|
|
goto fail;
|
|
|
|
ctx_drvdata = list_entry(priv->list_attached.next,
|
|
struct msm_iommu_ctx_drvdata, attached_elm);
|
|
iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
|
|
|
|
base = iommu_drvdata->base;
|
|
ctx = ctx_drvdata->num;
|
|
|
|
ret = __enable_clocks(iommu_drvdata);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
/* Invalidate context TLB */
|
|
SET_CTX_TLBIALL(base, ctx, 0);
|
|
SET_V2PPR(base, ctx, va & V2Pxx_VA);
|
|
|
|
par = GET_PAR(base, ctx);
|
|
|
|
/* We are dealing with a supersection */
|
|
if (GET_NOFAULT_SS(base, ctx))
|
|
ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
|
|
else /* Upper 20 bits from PAR, lower 12 from VA */
|
|
ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
|
|
|
|
if (GET_FAULT(base, ctx))
|
|
ret = 0;
|
|
|
|
__disable_clocks(iommu_drvdata);
|
|
fail:
|
|
spin_unlock_irqrestore(&msm_iommu_lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
static bool msm_iommu_capable(enum iommu_cap cap)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static void print_ctx_regs(void __iomem *base, int ctx)
|
|
{
|
|
unsigned int fsr = GET_FSR(base, ctx);
|
|
pr_err("FAR = %08x PAR = %08x\n",
|
|
GET_FAR(base, ctx), GET_PAR(base, ctx));
|
|
pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
|
|
(fsr & 0x02) ? "TF " : "",
|
|
(fsr & 0x04) ? "AFF " : "",
|
|
(fsr & 0x08) ? "APF " : "",
|
|
(fsr & 0x10) ? "TLBMF " : "",
|
|
(fsr & 0x20) ? "HTWDEEF " : "",
|
|
(fsr & 0x40) ? "HTWSEEF " : "",
|
|
(fsr & 0x80) ? "MHF " : "",
|
|
(fsr & 0x10000) ? "SL " : "",
|
|
(fsr & 0x40000000) ? "SS " : "",
|
|
(fsr & 0x80000000) ? "MULTI " : "");
|
|
|
|
pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
|
|
GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
|
|
pr_err("TTBR0 = %08x TTBR1 = %08x\n",
|
|
GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
|
|
pr_err("SCTLR = %08x ACTLR = %08x\n",
|
|
GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
|
|
pr_err("PRRR = %08x NMRR = %08x\n",
|
|
GET_PRRR(base, ctx), GET_NMRR(base, ctx));
|
|
}
|
|
|
|
irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
|
|
{
|
|
struct msm_iommu_drvdata *drvdata = dev_id;
|
|
void __iomem *base;
|
|
unsigned int fsr;
|
|
int i, ret;
|
|
|
|
spin_lock(&msm_iommu_lock);
|
|
|
|
if (!drvdata) {
|
|
pr_err("Invalid device ID in context interrupt handler\n");
|
|
goto fail;
|
|
}
|
|
|
|
base = drvdata->base;
|
|
|
|
pr_err("Unexpected IOMMU page fault!\n");
|
|
pr_err("base = %08x\n", (unsigned int) base);
|
|
|
|
ret = __enable_clocks(drvdata);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
for (i = 0; i < drvdata->ncb; i++) {
|
|
fsr = GET_FSR(base, i);
|
|
if (fsr) {
|
|
pr_err("Fault occurred in context %d.\n", i);
|
|
pr_err("Interesting registers:\n");
|
|
print_ctx_regs(base, i);
|
|
SET_FSR(base, i, 0x4000000F);
|
|
}
|
|
}
|
|
__disable_clocks(drvdata);
|
|
fail:
|
|
spin_unlock(&msm_iommu_lock);
|
|
return 0;
|
|
}
|
|
|
|
static const struct iommu_ops msm_iommu_ops = {
|
|
.capable = msm_iommu_capable,
|
|
.domain_alloc = msm_iommu_domain_alloc,
|
|
.domain_free = msm_iommu_domain_free,
|
|
.attach_dev = msm_iommu_attach_dev,
|
|
.detach_dev = msm_iommu_detach_dev,
|
|
.map = msm_iommu_map,
|
|
.unmap = msm_iommu_unmap,
|
|
.map_sg = default_iommu_map_sg,
|
|
.iova_to_phys = msm_iommu_iova_to_phys,
|
|
.pgsize_bitmap = MSM_IOMMU_PGSIZES,
|
|
};
|
|
|
|
static int __init get_tex_class(int icp, int ocp, int mt, int nos)
|
|
{
|
|
int i = 0;
|
|
unsigned int prrr = 0;
|
|
unsigned int nmrr = 0;
|
|
int c_icp, c_ocp, c_mt, c_nos;
|
|
|
|
RCP15_PRRR(prrr);
|
|
RCP15_NMRR(nmrr);
|
|
|
|
for (i = 0; i < NUM_TEX_CLASS; i++) {
|
|
c_nos = PRRR_NOS(prrr, i);
|
|
c_mt = PRRR_MT(prrr, i);
|
|
c_icp = NMRR_ICP(nmrr, i);
|
|
c_ocp = NMRR_OCP(nmrr, i);
|
|
|
|
if (icp == c_icp && ocp == c_ocp && c_mt == mt && c_nos == nos)
|
|
return i;
|
|
}
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
static void __init setup_iommu_tex_classes(void)
|
|
{
|
|
msm_iommu_tex_class[MSM_IOMMU_ATTR_NONCACHED] =
|
|
get_tex_class(CP_NONCACHED, CP_NONCACHED, MT_NORMAL, 1);
|
|
|
|
msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_WA] =
|
|
get_tex_class(CP_WB_WA, CP_WB_WA, MT_NORMAL, 1);
|
|
|
|
msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_NWA] =
|
|
get_tex_class(CP_WB_NWA, CP_WB_NWA, MT_NORMAL, 1);
|
|
|
|
msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WT] =
|
|
get_tex_class(CP_WT, CP_WT, MT_NORMAL, 1);
|
|
}
|
|
|
|
static int __init msm_iommu_init(void)
|
|
{
|
|
setup_iommu_tex_classes();
|
|
bus_set_iommu(&platform_bus_type, &msm_iommu_ops);
|
|
return 0;
|
|
}
|
|
|
|
subsys_initcall(msm_iommu_init);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
|