513 lines
13 KiB
C
513 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* DaVinci Power Management and Real Time Clock Driver for TI platforms
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*
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* Copyright (C) 2009 Texas Instruments, Inc
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*
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* Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/rtc.h>
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#include <linux/bcd.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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/*
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* The DaVinci RTC is a simple RTC with the following
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* Sec: 0 - 59 : BCD count
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* Min: 0 - 59 : BCD count
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* Hour: 0 - 23 : BCD count
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* Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
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*/
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/* PRTC interface registers */
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#define DAVINCI_PRTCIF_PID 0x00
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#define PRTCIF_CTLR 0x04
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#define PRTCIF_LDATA 0x08
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#define PRTCIF_UDATA 0x0C
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#define PRTCIF_INTEN 0x10
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#define PRTCIF_INTFLG 0x14
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/* PRTCIF_CTLR bit fields */
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#define PRTCIF_CTLR_BUSY BIT(31)
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#define PRTCIF_CTLR_SIZE BIT(25)
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#define PRTCIF_CTLR_DIR BIT(24)
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#define PRTCIF_CTLR_BENU_MSB BIT(23)
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#define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
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#define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
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#define PRTCIF_CTLR_BENU_LSB BIT(20)
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#define PRTCIF_CTLR_BENU_MASK (0x00F00000)
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#define PRTCIF_CTLR_BENL_MSB BIT(19)
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#define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
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#define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
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#define PRTCIF_CTLR_BENL_LSB BIT(16)
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#define PRTCIF_CTLR_BENL_MASK (0x000F0000)
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/* PRTCIF_INTEN bit fields */
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#define PRTCIF_INTEN_RTCSS BIT(1)
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#define PRTCIF_INTEN_RTCIF BIT(0)
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#define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
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| PRTCIF_INTEN_RTCIF)
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/* PRTCIF_INTFLG bit fields */
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#define PRTCIF_INTFLG_RTCSS BIT(1)
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#define PRTCIF_INTFLG_RTCIF BIT(0)
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#define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
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| PRTCIF_INTFLG_RTCIF)
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/* PRTC subsystem registers */
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#define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
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#define PRTCSS_RTC_CTRL (0x10)
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#define PRTCSS_RTC_WDT (0x11)
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#define PRTCSS_RTC_TMR0 (0x12)
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#define PRTCSS_RTC_TMR1 (0x13)
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#define PRTCSS_RTC_CCTRL (0x14)
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#define PRTCSS_RTC_SEC (0x15)
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#define PRTCSS_RTC_MIN (0x16)
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#define PRTCSS_RTC_HOUR (0x17)
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#define PRTCSS_RTC_DAY0 (0x18)
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#define PRTCSS_RTC_DAY1 (0x19)
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#define PRTCSS_RTC_AMIN (0x1A)
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#define PRTCSS_RTC_AHOUR (0x1B)
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#define PRTCSS_RTC_ADAY0 (0x1C)
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#define PRTCSS_RTC_ADAY1 (0x1D)
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#define PRTCSS_RTC_CLKC_CNT (0x20)
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/* PRTCSS_RTC_INTC_EXTENA1 */
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#define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
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/* PRTCSS_RTC_CTRL bit fields */
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#define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
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#define PRTCSS_RTC_CTRL_WEN BIT(6)
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#define PRTCSS_RTC_CTRL_WDRT BIT(5)
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#define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
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#define PRTCSS_RTC_CTRL_TE BIT(3)
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#define PRTCSS_RTC_CTRL_TIEN BIT(2)
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#define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
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#define PRTCSS_RTC_CTRL_TMMD BIT(0)
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/* PRTCSS_RTC_CCTRL bit fields */
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#define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
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#define PRTCSS_RTC_CCTRL_DAEN BIT(5)
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#define PRTCSS_RTC_CCTRL_HAEN BIT(4)
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#define PRTCSS_RTC_CCTRL_MAEN BIT(3)
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#define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
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#define PRTCSS_RTC_CCTRL_AIEN BIT(1)
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#define PRTCSS_RTC_CCTRL_CAEN BIT(0)
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static DEFINE_SPINLOCK(davinci_rtc_lock);
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struct davinci_rtc {
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struct rtc_device *rtc;
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void __iomem *base;
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int irq;
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};
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static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
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u32 val, u32 addr)
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{
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writel(val, davinci_rtc->base + addr);
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}
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static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
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{
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return readl(davinci_rtc->base + addr);
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}
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static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
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{
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while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
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cpu_relax();
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}
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static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
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unsigned long val, u8 addr)
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{
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rtcif_wait(davinci_rtc);
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rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
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rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
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rtcif_wait(davinci_rtc);
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}
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static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
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{
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rtcif_wait(davinci_rtc);
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rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
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PRTCIF_CTLR);
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rtcif_wait(davinci_rtc);
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return rtcif_read(davinci_rtc, PRTCIF_LDATA);
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}
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static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
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{
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while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
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PRTCSS_RTC_CCTRL_CALBUSY)
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cpu_relax();
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}
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static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
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{
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struct davinci_rtc *davinci_rtc = class_dev;
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unsigned long events = 0;
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u32 irq_flg;
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u8 alm_irq, tmr_irq;
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u8 rtc_ctrl, rtc_cctrl;
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int ret = IRQ_NONE;
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irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
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PRTCIF_INTFLG_RTCSS;
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alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
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PRTCSS_RTC_CCTRL_ALMFLG;
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tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
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PRTCSS_RTC_CTRL_TMRFLG;
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if (irq_flg) {
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if (alm_irq) {
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events |= RTC_IRQF | RTC_AF;
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rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
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rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
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rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
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} else if (tmr_irq) {
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events |= RTC_IRQF | RTC_PF;
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rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
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rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
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rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
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}
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rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
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PRTCIF_INTFLG);
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rtc_update_irq(davinci_rtc->rtc, 1, events);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static int
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davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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u8 rtc_ctrl;
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unsigned long flags;
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int ret = 0;
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spin_lock_irqsave(&davinci_rtc_lock, flags);
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rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
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switch (cmd) {
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case RTC_WIE_ON:
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rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
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break;
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case RTC_WIE_OFF:
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rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
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break;
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default:
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ret = -ENOIOCTLCMD;
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}
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rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
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spin_unlock_irqrestore(&davinci_rtc_lock, flags);
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return ret;
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}
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static void convertfromdays(u16 days, struct rtc_time *tm)
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{
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int tmp_days, year, mon;
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for (year = 2000;; year++) {
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tmp_days = rtc_year_days(1, 12, year);
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if (days >= tmp_days)
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days -= tmp_days;
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else {
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for (mon = 0;; mon++) {
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tmp_days = rtc_month_days(mon, year);
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if (days >= tmp_days) {
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days -= tmp_days;
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} else {
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tm->tm_year = year - 1900;
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tm->tm_mon = mon;
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tm->tm_mday = days + 1;
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break;
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}
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}
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break;
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}
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}
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}
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static void convert2days(u16 *days, struct rtc_time *tm)
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{
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int i;
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*days = 0;
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for (i = 2000; i < 1900 + tm->tm_year; i++)
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*days += rtc_year_days(1, 12, i);
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*days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
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}
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static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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u16 days = 0;
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u8 day0, day1;
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unsigned long flags;
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spin_lock_irqsave(&davinci_rtc_lock, flags);
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davinci_rtcss_calendar_wait(davinci_rtc);
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tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
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davinci_rtcss_calendar_wait(davinci_rtc);
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tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
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davinci_rtcss_calendar_wait(davinci_rtc);
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tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
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davinci_rtcss_calendar_wait(davinci_rtc);
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day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
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davinci_rtcss_calendar_wait(davinci_rtc);
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day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
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spin_unlock_irqrestore(&davinci_rtc_lock, flags);
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days |= day1;
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days <<= 8;
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days |= day0;
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convertfromdays(days, tm);
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return 0;
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}
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static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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u16 days;
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u8 rtc_cctrl;
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unsigned long flags;
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convert2days(&days, tm);
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spin_lock_irqsave(&davinci_rtc_lock, flags);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
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rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
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rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
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rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
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spin_unlock_irqrestore(&davinci_rtc_lock, flags);
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return 0;
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}
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static int davinci_rtc_alarm_irq_enable(struct device *dev,
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unsigned int enabled)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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unsigned long flags;
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u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
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spin_lock_irqsave(&davinci_rtc_lock, flags);
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if (enabled)
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rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
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PRTCSS_RTC_CCTRL_HAEN |
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PRTCSS_RTC_CCTRL_MAEN |
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PRTCSS_RTC_CCTRL_ALMFLG |
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PRTCSS_RTC_CCTRL_AIEN;
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else
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rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
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spin_unlock_irqrestore(&davinci_rtc_lock, flags);
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return 0;
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}
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static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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u16 days = 0;
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u8 day0, day1;
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unsigned long flags;
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alm->time.tm_sec = 0;
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spin_lock_irqsave(&davinci_rtc_lock, flags);
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davinci_rtcss_calendar_wait(davinci_rtc);
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alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
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davinci_rtcss_calendar_wait(davinci_rtc);
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alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
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davinci_rtcss_calendar_wait(davinci_rtc);
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day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
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davinci_rtcss_calendar_wait(davinci_rtc);
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day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
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spin_unlock_irqrestore(&davinci_rtc_lock, flags);
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days |= day1;
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days <<= 8;
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days |= day0;
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convertfromdays(days, &alm->time);
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alm->pending = !!(rtcss_read(davinci_rtc,
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PRTCSS_RTC_CCTRL) &
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PRTCSS_RTC_CCTRL_AIEN);
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alm->enabled = alm->pending && device_may_wakeup(dev);
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return 0;
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}
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static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
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{
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struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
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unsigned long flags;
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u16 days;
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convert2days(&days, &alm->time);
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spin_lock_irqsave(&davinci_rtc_lock, flags);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
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davinci_rtcss_calendar_wait(davinci_rtc);
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rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
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spin_unlock_irqrestore(&davinci_rtc_lock, flags);
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return 0;
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}
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static const struct rtc_class_ops davinci_rtc_ops = {
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.ioctl = davinci_rtc_ioctl,
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.read_time = davinci_rtc_read_time,
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.set_time = davinci_rtc_set_time,
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.alarm_irq_enable = davinci_rtc_alarm_irq_enable,
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.read_alarm = davinci_rtc_read_alarm,
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.set_alarm = davinci_rtc_set_alarm,
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};
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static int __init davinci_rtc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct davinci_rtc *davinci_rtc;
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int ret = 0;
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davinci_rtc = devm_kzalloc(&pdev->dev, sizeof(struct davinci_rtc), GFP_KERNEL);
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if (!davinci_rtc)
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return -ENOMEM;
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davinci_rtc->irq = platform_get_irq(pdev, 0);
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if (davinci_rtc->irq < 0)
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return davinci_rtc->irq;
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davinci_rtc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(davinci_rtc->base))
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return PTR_ERR(davinci_rtc->base);
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platform_set_drvdata(pdev, davinci_rtc);
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davinci_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
|
|
if (IS_ERR(davinci_rtc->rtc))
|
|
return PTR_ERR(davinci_rtc->rtc);
|
|
|
|
davinci_rtc->rtc->ops = &davinci_rtc_ops;
|
|
davinci_rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
|
|
davinci_rtc->rtc->range_max = RTC_TIMESTAMP_BEGIN_2000 + (1 << 16) * 86400ULL - 1;
|
|
|
|
rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
|
|
rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
|
|
rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
|
|
|
|
rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
|
|
rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
|
|
|
|
ret = devm_request_irq(dev, davinci_rtc->irq, davinci_rtc_interrupt,
|
|
0, "davinci_rtc", davinci_rtc);
|
|
if (ret < 0) {
|
|
dev_err(dev, "unable to register davinci RTC interrupt\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Enable interrupts */
|
|
rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
|
|
rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
|
|
PRTCSS_RTC_INTC_EXTENA1);
|
|
|
|
rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
|
|
|
|
device_init_wakeup(&pdev->dev, 0);
|
|
|
|
return devm_rtc_register_device(davinci_rtc->rtc);
|
|
}
|
|
|
|
static int __exit davinci_rtc_remove(struct platform_device *pdev)
|
|
{
|
|
struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
|
|
|
|
device_init_wakeup(&pdev->dev, 0);
|
|
|
|
rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver davinci_rtc_driver = {
|
|
.remove = __exit_p(davinci_rtc_remove),
|
|
.driver = {
|
|
.name = "rtc_davinci",
|
|
},
|
|
};
|
|
|
|
module_platform_driver_probe(davinci_rtc_driver, davinci_rtc_probe);
|
|
|
|
MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
|
|
MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
|
|
MODULE_LICENSE("GPL");
|