432 lines
9.7 KiB
C
432 lines
9.7 KiB
C
/*
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* IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
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*
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* Copyright 2007-2009 Analog Devices Inc.
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* Philippe Gerum <rpm@xenomai.org>
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*
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* Licensed under the GPL-2.
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/cache.h>
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#include <linux/clockchips.h>
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#include <linux/profile.h>
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#include <linux/errno.h>
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#include <linux/mm.h>
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#include <linux/cpu.h>
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#include <linux/smp.h>
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#include <linux/cpumask.h>
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#include <linux/seq_file.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/atomic.h>
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#include <asm/cacheflush.h>
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#include <asm/irq_handler.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/cpu.h>
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#include <asm/time.h>
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#include <linux/err.h>
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/*
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* Anomaly notes:
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* 05000120 - we always define corelock as 32-bit integer in L2
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*/
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struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
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#ifdef CONFIG_ICACHE_FLUSH_L1
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unsigned long blackfin_iflush_l1_entry[NR_CPUS];
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#endif
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struct blackfin_initial_pda initial_pda_coreb;
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enum ipi_message_type {
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BFIN_IPI_NONE,
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BFIN_IPI_TIMER,
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BFIN_IPI_RESCHEDULE,
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BFIN_IPI_CALL_FUNC,
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BFIN_IPI_CPU_STOP,
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};
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struct blackfin_flush_data {
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unsigned long start;
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unsigned long end;
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};
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void *secondary_stack;
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static struct blackfin_flush_data smp_flush_data;
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static DEFINE_SPINLOCK(stop_lock);
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/* A magic number - stress test shows this is safe for common cases */
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#define BFIN_IPI_MSGQ_LEN 5
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/* Simple FIFO buffer, overflow leads to panic */
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struct ipi_data {
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atomic_t count;
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atomic_t bits;
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};
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static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);
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static void ipi_cpu_stop(unsigned int cpu)
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{
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spin_lock(&stop_lock);
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printk(KERN_CRIT "CPU%u: stopping\n", cpu);
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dump_stack();
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spin_unlock(&stop_lock);
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set_cpu_online(cpu, false);
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local_irq_disable();
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while (1)
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SSYNC();
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}
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static void ipi_flush_icache(void *info)
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{
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struct blackfin_flush_data *fdata = info;
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/* Invalidate the memory holding the bounds of the flushed region. */
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blackfin_dcache_invalidate_range((unsigned long)fdata,
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(unsigned long)fdata + sizeof(*fdata));
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/* Make sure all write buffers in the data side of the core
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* are flushed before trying to invalidate the icache. This
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* needs to be after the data flush and before the icache
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* flush so that the SSYNC does the right thing in preventing
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* the instruction prefetcher from hitting things in cached
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* memory at the wrong time -- it runs much further ahead than
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* the pipeline.
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*/
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SSYNC();
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/* ipi_flaush_icache is invoked by generic flush_icache_range,
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* so call blackfin arch icache flush directly here.
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*/
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blackfin_icache_flush_range(fdata->start, fdata->end);
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}
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/* Use IRQ_SUPPLE_0 to request reschedule.
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* When returning from interrupt to user space,
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* there is chance to reschedule */
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static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
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{
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unsigned int cpu = smp_processor_id();
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platform_clear_ipi(cpu, IRQ_SUPPLE_0);
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return IRQ_HANDLED;
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}
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DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
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void ipi_timer(void)
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{
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int cpu = smp_processor_id();
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struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
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evt->event_handler(evt);
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}
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static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
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{
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struct ipi_data *bfin_ipi_data;
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unsigned int cpu = smp_processor_id();
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unsigned long pending;
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unsigned long msg;
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platform_clear_ipi(cpu, IRQ_SUPPLE_1);
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smp_rmb();
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bfin_ipi_data = this_cpu_ptr(&bfin_ipi);
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while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
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msg = 0;
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do {
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msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
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switch (msg) {
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case BFIN_IPI_TIMER:
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ipi_timer();
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break;
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case BFIN_IPI_RESCHEDULE:
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scheduler_ipi();
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break;
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case BFIN_IPI_CALL_FUNC:
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generic_smp_call_function_interrupt();
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break;
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case BFIN_IPI_CPU_STOP:
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ipi_cpu_stop(cpu);
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break;
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default:
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goto out;
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}
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atomic_dec(&bfin_ipi_data->count);
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} while (msg < BITS_PER_LONG);
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}
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out:
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return IRQ_HANDLED;
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}
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static void bfin_ipi_init(void)
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{
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unsigned int cpu;
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struct ipi_data *bfin_ipi_data;
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for_each_possible_cpu(cpu) {
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bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
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atomic_set(&bfin_ipi_data->bits, 0);
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atomic_set(&bfin_ipi_data->count, 0);
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}
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}
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void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
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{
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unsigned int cpu;
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struct ipi_data *bfin_ipi_data;
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unsigned long flags;
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local_irq_save(flags);
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for_each_cpu(cpu, cpumask) {
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bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
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atomic_or((1 << msg), &bfin_ipi_data->bits);
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atomic_inc(&bfin_ipi_data->count);
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}
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local_irq_restore(flags);
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smp_wmb();
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for_each_cpu(cpu, cpumask)
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platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
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}
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void arch_send_call_function_single_ipi(int cpu)
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{
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send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
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}
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void arch_send_call_function_ipi_mask(const struct cpumask *mask)
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{
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send_ipi(mask, BFIN_IPI_CALL_FUNC);
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}
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void smp_send_reschedule(int cpu)
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{
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send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);
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return;
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}
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void smp_send_msg(const struct cpumask *mask, unsigned long type)
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{
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send_ipi(mask, type);
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}
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void smp_timer_broadcast(const struct cpumask *mask)
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{
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smp_send_msg(mask, BFIN_IPI_TIMER);
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}
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void smp_send_stop(void)
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{
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cpumask_t callmap;
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preempt_disable();
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cpumask_copy(&callmap, cpu_online_mask);
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cpumask_clear_cpu(smp_processor_id(), &callmap);
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if (!cpumask_empty(&callmap))
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send_ipi(&callmap, BFIN_IPI_CPU_STOP);
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preempt_enable();
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return;
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}
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int __cpu_up(unsigned int cpu, struct task_struct *idle)
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{
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int ret;
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secondary_stack = task_stack_page(idle) + THREAD_SIZE;
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ret = platform_boot_secondary(cpu, idle);
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secondary_stack = NULL;
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return ret;
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}
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static void setup_secondary(unsigned int cpu)
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{
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unsigned long ilat;
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bfin_write_IMASK(0);
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CSYNC();
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ilat = bfin_read_ILAT();
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CSYNC();
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bfin_write_ILAT(ilat);
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CSYNC();
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/* Enable interrupt levels IVG7-15. IARs have been already
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* programmed by the boot CPU. */
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bfin_irq_flags |= IMASK_IVG15 |
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IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
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IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
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}
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void secondary_start_kernel(void)
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{
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unsigned int cpu = smp_processor_id();
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struct mm_struct *mm = &init_mm;
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if (_bfin_swrst & SWRST_DBL_FAULT_B) {
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printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
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#ifdef CONFIG_DEBUG_DOUBLEFAULT
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printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
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initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
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initial_pda_coreb.retx_doublefault);
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printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
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initial_pda_coreb.dcplb_doublefault_addr);
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printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
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initial_pda_coreb.icplb_doublefault_addr);
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#endif
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printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
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initial_pda_coreb.retx);
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}
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/*
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* We want the D-cache to be enabled early, in case the atomic
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* support code emulates cache coherence (see
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* __ARCH_SYNC_CORE_DCACHE).
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*/
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init_exception_vectors();
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local_irq_disable();
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/* Attach the new idle task to the global mm. */
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atomic_inc(&mm->mm_users);
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atomic_inc(&mm->mm_count);
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current->active_mm = mm;
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preempt_disable();
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setup_secondary(cpu);
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platform_secondary_init(cpu);
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/* setup local core timer */
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bfin_local_timer_setup();
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local_irq_enable();
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bfin_setup_caches(cpu);
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notify_cpu_starting(cpu);
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/*
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* Calibrate loops per jiffy value.
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* IRQs need to be enabled here - D-cache can be invalidated
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* in timer irq handler, so core B can read correct jiffies.
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*/
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calibrate_delay();
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/* We are done with local CPU inits, unblock the boot CPU. */
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set_cpu_online(cpu, true);
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cpu_startup_entry(CPUHP_ONLINE);
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}
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void __init smp_prepare_boot_cpu(void)
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{
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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platform_prepare_cpus(max_cpus);
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bfin_ipi_init();
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platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
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platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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unsigned long bogosum = 0;
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unsigned int cpu;
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for_each_online_cpu(cpu)
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bogosum += loops_per_jiffy;
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printk(KERN_INFO "SMP: Total of %d processors activated "
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"(%lu.%02lu BogoMIPS).\n",
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num_online_cpus(),
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bogosum / (500000/HZ),
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(bogosum / (5000/HZ)) % 100);
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}
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void smp_icache_flush_range_others(unsigned long start, unsigned long end)
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{
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smp_flush_data.start = start;
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smp_flush_data.end = end;
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preempt_disable();
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if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
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printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
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preempt_enable();
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}
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EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
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#ifdef __ARCH_SYNC_CORE_ICACHE
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unsigned long icache_invld_count[NR_CPUS];
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void resync_core_icache(void)
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{
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unsigned int cpu = get_cpu();
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blackfin_invalidate_entire_icache();
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icache_invld_count[cpu]++;
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put_cpu();
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}
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EXPORT_SYMBOL(resync_core_icache);
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#endif
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#ifdef __ARCH_SYNC_CORE_DCACHE
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unsigned long dcache_invld_count[NR_CPUS];
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unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
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void resync_core_dcache(void)
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{
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unsigned int cpu = get_cpu();
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blackfin_invalidate_entire_dcache();
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dcache_invld_count[cpu]++;
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put_cpu();
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}
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EXPORT_SYMBOL(resync_core_dcache);
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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int __cpu_disable(void)
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{
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unsigned int cpu = smp_processor_id();
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if (cpu == 0)
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return -EPERM;
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set_cpu_online(cpu, false);
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return 0;
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}
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int __cpu_die(unsigned int cpu)
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{
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return cpu_wait_death(cpu, 5);
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}
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void cpu_die(void)
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{
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(void)cpu_report_death();
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atomic_dec(&init_mm.mm_users);
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atomic_dec(&init_mm.mm_count);
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local_irq_disable();
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platform_cpu_die();
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}
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#endif
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