Thierry Reding 4ee8cee0c5 drm/tegra: hdmi: Registers are 32-bit ... Use a sized unsigned 32-bit data type (u32) to store register contents. The HDMI registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>		2015-01-27 10:14:37 +01:00
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drm	drm/tegra: hdmi: Registers are 32-bit	2015-01-27 10:14:37 +01:00
host1x	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00
ipu-v3	gpu: ipu-di: Switch to DIV_ROUND_CLOSEST for DI clock divider calc	2015-01-07 19:15:04 +01:00
vga	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2014-10-13 16:23:15 +02:00
Makefile	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00