721 lines
24 KiB
C
721 lines
24 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/* idt8a340_reg.h
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*
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* Originally generated by regen.tcl on Thu Feb 14 19:23:44 PST 2019
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* https://github.com/richardcochran/regen
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*
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* Hand modified to include some HW registers.
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* Based on 4.8.0, SCSR rev C commit a03c7ae5
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*/
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#ifndef HAVE_IDT8A340_REG
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#define HAVE_IDT8A340_REG
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#define PAGE_ADDR_BASE 0x0000
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#define PAGE_ADDR 0x00fc
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#define HW_REVISION 0x8180
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#define REV_ID 0x007a
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#define HW_DPLL_0 (0x8a00)
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#define HW_DPLL_1 (0x8b00)
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#define HW_DPLL_2 (0x8c00)
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#define HW_DPLL_3 (0x8d00)
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#define HW_DPLL_4 (0x8e00)
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#define HW_DPLL_5 (0x8f00)
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#define HW_DPLL_6 (0x9000)
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#define HW_DPLL_7 (0x9100)
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#define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080)
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#define HW_DPLL_TOD_CTRL_1 (0x089)
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#define HW_DPLL_TOD_CTRL_2 (0x08A)
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#define HW_DPLL_TOD_OVR__0 (0x098)
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#define HW_DPLL_TOD_OUT_0__0 (0x0B0)
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#define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740)
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#define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741)
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#define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742)
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#define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743)
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#define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744)
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#define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745)
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#define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746)
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#define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747)
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#define HW_Q8_CH_SYNC_CTRL_0 (0xa748)
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#define HW_Q8_CH_SYNC_CTRL_1 (0xa749)
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#define HW_Q9_CH_SYNC_CTRL_0 (0xa74a)
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#define HW_Q9_CH_SYNC_CTRL_1 (0xa74b)
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#define HW_Q10_CH_SYNC_CTRL_0 (0xa74c)
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#define HW_Q10_CH_SYNC_CTRL_1 (0xa74d)
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#define HW_Q11_CH_SYNC_CTRL_0 (0xa74e)
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#define HW_Q11_CH_SYNC_CTRL_1 (0xa74f)
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#define SYNC_SOURCE_DPLL0_TOD_PPS 0x14
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#define SYNC_SOURCE_DPLL1_TOD_PPS 0x15
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#define SYNC_SOURCE_DPLL2_TOD_PPS 0x16
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#define SYNC_SOURCE_DPLL3_TOD_PPS 0x17
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#define SYNCTRL1_MASTER_SYNC_RST BIT(7)
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#define SYNCTRL1_MASTER_SYNC_TRIG BIT(5)
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#define SYNCTRL1_TOD_SYNC_TRIG BIT(4)
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#define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3)
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#define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2)
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#define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1)
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#define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0)
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#define HW_Q8_CTRL_SPARE (0xa7d4)
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#define HW_Q11_CTRL_SPARE (0xa7ec)
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/**
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* Select FOD5 as sync_trigger for Q8 divider.
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* Transition from logic zero to one
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* sets trigger to sync Q8 divider.
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*
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* Unused when FOD4 is driving Q8 divider (normal operation).
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*/
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#define Q9_TO_Q8_SYNC_TRIG BIT(1)
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/**
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* Enable FOD5 as driver for clock and sync for Q8 divider.
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* Enable fanout buffer for FOD5.
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*
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* Unused when FOD4 is driving Q8 divider (normal operation).
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*/
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#define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
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/**
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* Select FOD6 as sync_trigger for Q11 divider.
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* Transition from logic zero to one
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* sets trigger to sync Q11 divider.
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*
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* Unused when FOD7 is driving Q11 divider (normal operation).
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*/
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#define Q10_TO_Q11_SYNC_TRIG BIT(1)
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/**
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* Enable FOD6 as driver for clock and sync for Q11 divider.
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* Enable fanout buffer for FOD6.
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*
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* Unused when FOD7 is driving Q11 divider (normal operation).
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*/
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#define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
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#define RESET_CTRL 0xc000
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#define SM_RESET 0x0012
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#define SM_RESET_CMD 0x5A
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#define GENERAL_STATUS 0xc014
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#define BOOT_STATUS 0x0000
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#define HW_REV_ID 0x000A
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#define BOND_ID 0x000B
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#define HW_CSR_ID 0x000C
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#define HW_IRQ_ID 0x000E
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#define MAJ_REL 0x0010
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#define MIN_REL 0x0011
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#define HOTFIX_REL 0x0012
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#define PIPELINE_ID 0x0014
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#define BUILD_ID 0x0018
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#define JTAG_DEVICE_ID 0x001c
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#define PRODUCT_ID 0x001e
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#define OTP_SCSR_CONFIG_SELECT 0x0022
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#define STATUS 0xc03c
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#define DPLL_SYS_STATUS 0x0020
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#define DPLL_SYS_APLL_STATUS 0x0021
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#define USER_GPIO0_TO_7_STATUS 0x008a
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#define USER_GPIO8_TO_15_STATUS 0x008b
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#define GPIO_USER_CONTROL 0xc160
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#define GPIO0_TO_7_OUT 0x0000
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#define GPIO8_TO_15_OUT 0x0001
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#define STICKY_STATUS_CLEAR 0xc164
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#define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c
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#define ALERT_CFG 0xc188
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#define SYS_DPLL_XO 0xc194
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#define SYS_APLL 0xc19c
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#define INPUT_0 0xc1b0
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#define INPUT_1 0xc1c0
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#define INPUT_2 0xc1d0
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#define INPUT_3 0xc200
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#define INPUT_4 0xc210
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#define INPUT_5 0xc220
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#define INPUT_6 0xc230
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#define INPUT_7 0xc240
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#define INPUT_8 0xc250
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#define INPUT_9 0xc260
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#define INPUT_10 0xc280
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#define INPUT_11 0xc290
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#define INPUT_12 0xc2a0
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#define INPUT_13 0xc2b0
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#define INPUT_14 0xc2c0
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#define INPUT_15 0xc2d0
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#define REF_MON_0 0xc2e0
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#define REF_MON_1 0xc2ec
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#define REF_MON_2 0xc300
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#define REF_MON_3 0xc30c
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#define REF_MON_4 0xc318
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#define REF_MON_5 0xc324
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#define REF_MON_6 0xc330
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#define REF_MON_7 0xc33c
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#define REF_MON_8 0xc348
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#define REF_MON_9 0xc354
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#define REF_MON_10 0xc360
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#define REF_MON_11 0xc36c
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#define REF_MON_12 0xc380
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#define REF_MON_13 0xc38c
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#define REF_MON_14 0xc398
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#define REF_MON_15 0xc3a4
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#define DPLL_0 0xc3b0
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#define DPLL_CTRL_REG_0 0x0002
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#define DPLL_CTRL_REG_1 0x0003
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#define DPLL_CTRL_REG_2 0x0004
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#define DPLL_TOD_SYNC_CFG 0x0031
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#define DPLL_COMBO_SLAVE_CFG_0 0x0032
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#define DPLL_COMBO_SLAVE_CFG_1 0x0033
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#define DPLL_SLAVE_REF_CFG 0x0034
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#define DPLL_REF_MODE 0x0035
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#define DPLL_PHASE_MEASUREMENT_CFG 0x0036
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#define DPLL_MODE 0x0037
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#define DPLL_1 0xc400
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#define DPLL_2 0xc438
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#define DPLL_3 0xc480
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#define DPLL_4 0xc4b8
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#define DPLL_5 0xc500
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#define DPLL_6 0xc538
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#define DPLL_7 0xc580
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#define SYS_DPLL 0xc5b8
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#define DPLL_CTRL_0 0xc600
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#define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001
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#define DPLL_CTRL_COMBO_MASTER_CFG 0x003a
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#define DPLL_CTRL_1 0xc63c
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#define DPLL_CTRL_2 0xc680
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#define DPLL_CTRL_3 0xc6bc
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#define DPLL_CTRL_4 0xc700
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#define DPLL_CTRL_5 0xc73c
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#define DPLL_CTRL_6 0xc780
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#define DPLL_CTRL_7 0xc7bc
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#define SYS_DPLL_CTRL 0xc800
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#define DPLL_PHASE_0 0xc818
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/* Signed 42-bit FFO in units of 2^(-53) */
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#define DPLL_WR_PHASE 0x0000
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#define DPLL_PHASE_1 0xc81c
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#define DPLL_PHASE_2 0xc820
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#define DPLL_PHASE_3 0xc824
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#define DPLL_PHASE_4 0xc828
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#define DPLL_PHASE_5 0xc82c
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#define DPLL_PHASE_6 0xc830
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#define DPLL_PHASE_7 0xc834
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#define DPLL_FREQ_0 0xc838
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/* Signed 42-bit FFO in units of 2^(-53) */
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#define DPLL_WR_FREQ 0x0000
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#define DPLL_FREQ_1 0xc840
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#define DPLL_FREQ_2 0xc848
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#define DPLL_FREQ_3 0xc850
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#define DPLL_FREQ_4 0xc858
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#define DPLL_FREQ_5 0xc860
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#define DPLL_FREQ_6 0xc868
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#define DPLL_FREQ_7 0xc870
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#define DPLL_PHASE_PULL_IN_0 0xc880
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#define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */
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#define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */
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#define PULL_IN_CTRL 0x0007
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#define DPLL_PHASE_PULL_IN_1 0xc888
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#define DPLL_PHASE_PULL_IN_2 0xc890
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#define DPLL_PHASE_PULL_IN_3 0xc898
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#define DPLL_PHASE_PULL_IN_4 0xc8a0
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#define DPLL_PHASE_PULL_IN_5 0xc8a8
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#define DPLL_PHASE_PULL_IN_6 0xc8b0
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#define DPLL_PHASE_PULL_IN_7 0xc8b8
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#define GPIO_CFG 0xc8c0
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#define GPIO_CFG_GBL 0x0000
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#define GPIO_0 0xc8c2
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#define GPIO_DCO_INC_DEC 0x0000
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#define GPIO_OUT_CTRL_0 0x0001
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#define GPIO_OUT_CTRL_1 0x0002
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#define GPIO_TOD_TRIG 0x0003
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#define GPIO_DPLL_INDICATOR 0x0004
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#define GPIO_LOS_INDICATOR 0x0005
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#define GPIO_REF_INPUT_DSQ_0 0x0006
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#define GPIO_REF_INPUT_DSQ_1 0x0007
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#define GPIO_REF_INPUT_DSQ_2 0x0008
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#define GPIO_REF_INPUT_DSQ_3 0x0009
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#define GPIO_MAN_CLK_SEL_0 0x000a
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#define GPIO_MAN_CLK_SEL_1 0x000b
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#define GPIO_MAN_CLK_SEL_2 0x000c
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#define GPIO_SLAVE 0x000d
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#define GPIO_ALERT_OUT_CFG 0x000e
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#define GPIO_TOD_NOTIFICATION_CFG 0x000f
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#define GPIO_CTRL 0x0010
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#define GPIO_1 0xc8d4
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#define GPIO_2 0xc8e6
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#define GPIO_3 0xc900
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#define GPIO_4 0xc912
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#define GPIO_5 0xc924
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#define GPIO_6 0xc936
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#define GPIO_7 0xc948
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#define GPIO_8 0xc95a
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#define GPIO_9 0xc980
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#define GPIO_10 0xc992
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#define GPIO_11 0xc9a4
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#define GPIO_12 0xc9b6
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#define GPIO_13 0xc9c8
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#define GPIO_14 0xc9da
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#define GPIO_15 0xca00
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#define OUT_DIV_MUX 0xca12
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#define OUTPUT_0 0xca14
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/* FOD frequency output divider value */
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#define OUT_DIV 0x0000
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#define OUT_DUTY_CYCLE_HIGH 0x0004
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#define OUT_CTRL_0 0x0008
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#define OUT_CTRL_1 0x0009
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/* Phase adjustment in FOD cycles */
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#define OUT_PHASE_ADJ 0x000c
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#define OUTPUT_1 0xca24
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#define OUTPUT_2 0xca34
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#define OUTPUT_3 0xca44
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#define OUTPUT_4 0xca54
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#define OUTPUT_5 0xca64
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#define OUTPUT_6 0xca80
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#define OUTPUT_7 0xca90
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#define OUTPUT_8 0xcaa0
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#define OUTPUT_9 0xcab0
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#define OUTPUT_10 0xcac0
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#define OUTPUT_11 0xcad0
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#define SERIAL 0xcae0
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#define PWM_ENCODER_0 0xcb00
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#define PWM_ENCODER_1 0xcb08
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#define PWM_ENCODER_2 0xcb10
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#define PWM_ENCODER_3 0xcb18
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#define PWM_ENCODER_4 0xcb20
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#define PWM_ENCODER_5 0xcb28
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#define PWM_ENCODER_6 0xcb30
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#define PWM_ENCODER_7 0xcb38
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#define PWM_DECODER_0 0xcb40
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#define PWM_DECODER_1 0xcb48
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#define PWM_DECODER_2 0xcb50
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#define PWM_DECODER_3 0xcb58
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#define PWM_DECODER_4 0xcb60
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#define PWM_DECODER_5 0xcb68
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#define PWM_DECODER_6 0xcb70
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#define PWM_DECODER_7 0xcb80
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#define PWM_DECODER_8 0xcb88
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#define PWM_DECODER_9 0xcb90
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#define PWM_DECODER_10 0xcb98
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#define PWM_DECODER_11 0xcba0
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#define PWM_DECODER_12 0xcba8
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#define PWM_DECODER_13 0xcbb0
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#define PWM_DECODER_14 0xcbb8
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#define PWM_DECODER_15 0xcbc0
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#define PWM_USER_DATA 0xcbc8
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#define TOD_0 0xcbcc
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/* Enable TOD counter, output channel sync and even-PPS mode */
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#define TOD_CFG 0x0000
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#define TOD_1 0xcbce
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#define TOD_2 0xcbd0
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#define TOD_3 0xcbd2
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#define TOD_WRITE_0 0xcc00
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/* 8-bit subns, 32-bit ns, 48-bit seconds */
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#define TOD_WRITE 0x0000
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/* Counter increments after TOD write is completed */
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#define TOD_WRITE_COUNTER 0x000c
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/* TOD write trigger configuration */
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#define TOD_WRITE_SELECT_CFG_0 0x000d
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/* TOD write trigger selection */
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#define TOD_WRITE_CMD 0x000f
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#define TOD_WRITE_1 0xcc10
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#define TOD_WRITE_2 0xcc20
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#define TOD_WRITE_3 0xcc30
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#define TOD_READ_PRIMARY_0 0xcc40
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/* 8-bit subns, 32-bit ns, 48-bit seconds */
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#define TOD_READ_PRIMARY 0x0000
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/* Counter increments after TOD write is completed */
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#define TOD_READ_PRIMARY_COUNTER 0x000b
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/* Read trigger configuration */
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#define TOD_READ_PRIMARY_SEL_CFG_0 0x000c
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/* Read trigger selection */
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#define TOD_READ_PRIMARY_CMD 0x000e
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#define TOD_READ_PRIMARY_1 0xcc50
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#define TOD_READ_PRIMARY_2 0xcc60
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#define TOD_READ_PRIMARY_3 0xcc80
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#define TOD_READ_SECONDARY_0 0xcc90
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#define TOD_READ_SECONDARY_1 0xcca0
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#define TOD_READ_SECONDARY_2 0xccb0
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#define TOD_READ_SECONDARY_3 0xccc0
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#define OUTPUT_TDC_CFG 0xccd0
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#define OUTPUT_TDC_0 0xcd00
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#define OUTPUT_TDC_1 0xcd08
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#define OUTPUT_TDC_2 0xcd10
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#define OUTPUT_TDC_3 0xcd18
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#define INPUT_TDC 0xcd20
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#define SCRATCH 0xcf50
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#define EEPROM 0xcf68
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#define OTP 0xcf70
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#define BYTE 0xcf80
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/* Bit definitions for the MAJ_REL register */
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#define MAJOR_SHIFT (1)
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#define MAJOR_MASK (0x7f)
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#define PR_BUILD BIT(0)
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/* Bit definitions for the USER_GPIO0_TO_7_STATUS register */
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#define GPIO0_LEVEL BIT(0)
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#define GPIO1_LEVEL BIT(1)
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#define GPIO2_LEVEL BIT(2)
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#define GPIO3_LEVEL BIT(3)
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#define GPIO4_LEVEL BIT(4)
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#define GPIO5_LEVEL BIT(5)
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#define GPIO6_LEVEL BIT(6)
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#define GPIO7_LEVEL BIT(7)
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/* Bit definitions for the USER_GPIO8_TO_15_STATUS register */
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#define GPIO8_LEVEL BIT(0)
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#define GPIO9_LEVEL BIT(1)
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#define GPIO10_LEVEL BIT(2)
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#define GPIO11_LEVEL BIT(3)
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#define GPIO12_LEVEL BIT(4)
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#define GPIO13_LEVEL BIT(5)
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#define GPIO14_LEVEL BIT(6)
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#define GPIO15_LEVEL BIT(7)
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/* Bit definitions for the GPIO0_TO_7_OUT register */
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#define GPIO0_DRIVE_LEVEL BIT(0)
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#define GPIO1_DRIVE_LEVEL BIT(1)
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#define GPIO2_DRIVE_LEVEL BIT(2)
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#define GPIO3_DRIVE_LEVEL BIT(3)
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#define GPIO4_DRIVE_LEVEL BIT(4)
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#define GPIO5_DRIVE_LEVEL BIT(5)
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#define GPIO6_DRIVE_LEVEL BIT(6)
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#define GPIO7_DRIVE_LEVEL BIT(7)
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/* Bit definitions for the GPIO8_TO_15_OUT register */
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#define GPIO8_DRIVE_LEVEL BIT(0)
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#define GPIO9_DRIVE_LEVEL BIT(1)
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#define GPIO10_DRIVE_LEVEL BIT(2)
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#define GPIO11_DRIVE_LEVEL BIT(3)
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#define GPIO12_DRIVE_LEVEL BIT(4)
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#define GPIO13_DRIVE_LEVEL BIT(5)
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#define GPIO14_DRIVE_LEVEL BIT(6)
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#define GPIO15_DRIVE_LEVEL BIT(7)
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/* Bit definitions for the DPLL_TOD_SYNC_CFG register */
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#define TOD_SYNC_SOURCE_SHIFT (1)
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#define TOD_SYNC_SOURCE_MASK (0x3)
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#define TOD_SYNC_EN BIT(0)
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/* Bit definitions for the DPLL_MODE register */
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#define WRITE_TIMER_MODE BIT(6)
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#define PLL_MODE_SHIFT (3)
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#define PLL_MODE_MASK (0x7)
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#define STATE_MODE_SHIFT (0)
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#define STATE_MODE_MASK (0x7)
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/* Bit definitions for the GPIO_CFG_GBL register */
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#define SUPPLY_MODE_SHIFT (0)
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#define SUPPLY_MODE_MASK (0x3)
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/* Bit definitions for the GPIO_DCO_INC_DEC register */
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#define INCDEC_DPLL_INDEX_SHIFT (0)
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#define INCDEC_DPLL_INDEX_MASK (0x7)
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/* Bit definitions for the GPIO_OUT_CTRL_0 register */
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#define CTRL_OUT_0 BIT(0)
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#define CTRL_OUT_1 BIT(1)
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#define CTRL_OUT_2 BIT(2)
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#define CTRL_OUT_3 BIT(3)
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#define CTRL_OUT_4 BIT(4)
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#define CTRL_OUT_5 BIT(5)
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#define CTRL_OUT_6 BIT(6)
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#define CTRL_OUT_7 BIT(7)
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/* Bit definitions for the GPIO_OUT_CTRL_1 register */
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#define CTRL_OUT_8 BIT(0)
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#define CTRL_OUT_9 BIT(1)
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#define CTRL_OUT_10 BIT(2)
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#define CTRL_OUT_11 BIT(3)
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#define CTRL_OUT_12 BIT(4)
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#define CTRL_OUT_13 BIT(5)
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#define CTRL_OUT_14 BIT(6)
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#define CTRL_OUT_15 BIT(7)
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/* Bit definitions for the GPIO_TOD_TRIG register */
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#define TOD_TRIG_0 BIT(0)
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#define TOD_TRIG_1 BIT(1)
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#define TOD_TRIG_2 BIT(2)
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#define TOD_TRIG_3 BIT(3)
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/* Bit definitions for the GPIO_DPLL_INDICATOR register */
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#define IND_DPLL_INDEX_SHIFT (0)
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#define IND_DPLL_INDEX_MASK (0x7)
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/* Bit definitions for the GPIO_LOS_INDICATOR register */
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#define REFMON_INDEX_SHIFT (0)
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#define REFMON_INDEX_MASK (0xf)
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/* Active level of LOS indicator, 0=low 1=high */
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#define ACTIVE_LEVEL BIT(4)
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/* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */
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#define DSQ_INP_0 BIT(0)
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#define DSQ_INP_1 BIT(1)
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#define DSQ_INP_2 BIT(2)
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#define DSQ_INP_3 BIT(3)
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#define DSQ_INP_4 BIT(4)
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#define DSQ_INP_5 BIT(5)
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#define DSQ_INP_6 BIT(6)
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#define DSQ_INP_7 BIT(7)
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/* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */
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#define DSQ_INP_8 BIT(0)
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#define DSQ_INP_9 BIT(1)
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#define DSQ_INP_10 BIT(2)
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#define DSQ_INP_11 BIT(3)
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#define DSQ_INP_12 BIT(4)
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#define DSQ_INP_13 BIT(5)
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#define DSQ_INP_14 BIT(6)
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#define DSQ_INP_15 BIT(7)
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/* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */
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#define DSQ_DPLL_0 BIT(0)
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#define DSQ_DPLL_1 BIT(1)
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#define DSQ_DPLL_2 BIT(2)
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#define DSQ_DPLL_3 BIT(3)
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#define DSQ_DPLL_4 BIT(4)
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#define DSQ_DPLL_5 BIT(5)
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#define DSQ_DPLL_6 BIT(6)
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#define DSQ_DPLL_7 BIT(7)
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/* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */
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#define DSQ_DPLL_SYS BIT(0)
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#define GPIO_DSQ_LEVEL BIT(1)
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/* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */
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#define DPLL_TOD_SHIFT (0)
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#define DPLL_TOD_MASK (0x3)
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#define TOD_READ_SECONDARY BIT(2)
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#define GPIO_ASSERT_LEVEL BIT(3)
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/* Bit definitions for the GPIO_CTRL register */
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#define GPIO_FUNCTION_EN BIT(0)
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#define GPIO_CMOS_OD_MODE BIT(1)
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#define GPIO_CONTROL_DIR BIT(2)
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#define GPIO_PU_PD_MODE BIT(3)
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#define GPIO_FUNCTION_SHIFT (4)
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#define GPIO_FUNCTION_MASK (0xf)
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/* Bit definitions for the OUT_CTRL_1 register */
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#define OUT_SYNC_DISABLE BIT(7)
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#define SQUELCH_VALUE BIT(6)
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#define SQUELCH_DISABLE BIT(5)
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#define PAD_VDDO_SHIFT (2)
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#define PAD_VDDO_MASK (0x7)
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#define PAD_CMOSDRV_SHIFT (0)
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#define PAD_CMOSDRV_MASK (0x3)
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/* Bit definitions for the TOD_CFG register */
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#define TOD_EVEN_PPS_MODE BIT(2)
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#define TOD_OUT_SYNC_ENABLE BIT(1)
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#define TOD_ENABLE BIT(0)
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/* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */
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#define WR_PWM_DECODER_INDEX_SHIFT (4)
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#define WR_PWM_DECODER_INDEX_MASK (0xf)
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#define WR_REF_INDEX_SHIFT (0)
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#define WR_REF_INDEX_MASK (0xf)
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/* Bit definitions for the TOD_WRITE_CMD register */
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#define TOD_WRITE_SELECTION_SHIFT (0)
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#define TOD_WRITE_SELECTION_MASK (0xf)
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/* 4.8.7 */
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#define TOD_WRITE_TYPE_SHIFT (4)
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#define TOD_WRITE_TYPE_MASK (0x3)
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/* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
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#define RD_PWM_DECODER_INDEX_SHIFT (4)
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#define RD_PWM_DECODER_INDEX_MASK (0xf)
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#define RD_REF_INDEX_SHIFT (0)
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#define RD_REF_INDEX_MASK (0xf)
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/* Bit definitions for the TOD_READ_PRIMARY_CMD register */
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#define TOD_READ_TRIGGER_MODE BIT(4)
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#define TOD_READ_TRIGGER_SHIFT (0)
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#define TOD_READ_TRIGGER_MASK (0xf)
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/* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */
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#define COMBO_MASTER_HOLD BIT(0)
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/* Bit definitions for DPLL_SYS_STATUS register */
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#define DPLL_SYS_STATE_MASK (0xf)
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/* Bit definitions for SYS_APLL_STATUS register */
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#define SYS_APLL_LOSS_LOCK_LIVE_MASK BIT(0)
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#define SYS_APLL_LOSS_LOCK_LIVE_LOCKED 0
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#define SYS_APLL_LOSS_LOCK_LIVE_UNLOCKED 1
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#endif
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