348 lines
9.3 KiB
C
348 lines
9.3 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Ke Yu
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* Zhiyuan Lv <zhiyuan.lv@intel.com>
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*
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* Contributors:
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* Terrence Xu <terrence.xu@intel.com>
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* Changbin Du <changbin.du@intel.com>
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* Bing Niu <bing.niu@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "gvt.h"
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static int get_edp_pipe(struct intel_vgpu *vgpu)
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{
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u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
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int pipe = -1;
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switch (data & TRANS_DDI_EDP_INPUT_MASK) {
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case TRANS_DDI_EDP_INPUT_A_ON:
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case TRANS_DDI_EDP_INPUT_A_ONOFF:
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pipe = PIPE_A;
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break;
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case TRANS_DDI_EDP_INPUT_B_ONOFF:
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pipe = PIPE_B;
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break;
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case TRANS_DDI_EDP_INPUT_C_ONOFF:
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pipe = PIPE_C;
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break;
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}
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return pipe;
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}
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static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
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return 0;
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if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
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return 0;
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return 1;
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}
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static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
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return -EINVAL;
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if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
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return 1;
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if (edp_pipe_is_enabled(vgpu) &&
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get_edp_pipe(vgpu) == pipe)
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return 1;
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return 0;
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}
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/* EDID with 1920x1200 as its resolution */
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static unsigned char virtual_dp_monitor_edid[] = {
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/*Header*/
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0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
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/* Vendor & Product Identification */
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0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
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/* Version & Revision */
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0x01, 0x04,
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/* Basic Display Parameters & Features */
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0xa5, 0x34, 0x20, 0x78, 0x23,
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/* Color Characteristics */
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0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
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/* Established Timings: maximum resolution is 1024x768 */
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0x21, 0x08, 0x00,
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/*
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* Standard Timings.
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* below new resolutions can be supported:
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* 1920x1080, 1280x720, 1280x960, 1280x1024,
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* 1440x900, 1600x1200, 1680x1050
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*/
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0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
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0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
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/* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
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0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
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0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
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/* 18 Byte Data Blocks 2: invalid */
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0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
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0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
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/* 18 Byte Data Blocks 3: invalid */
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0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
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0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
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/* 18 Byte Data Blocks 4: invalid */
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0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
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0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
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/* Extension Block Count */
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0x00,
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/* Checksum */
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0x45,
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};
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#define DPCD_HEADER_SIZE 0xb
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static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
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0x11, 0x0a, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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};
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static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
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SDE_PORTC_HOTPLUG_CPT |
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SDE_PORTD_HOTPLUG_CPT);
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if (IS_SKYLAKE(dev_priv))
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vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
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SDE_PORTE_HOTPLUG_SPT);
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if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B))
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vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
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if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C))
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vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
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if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D))
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vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
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if (IS_SKYLAKE(dev_priv) &&
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intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
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vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
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}
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if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
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if (IS_BROADWELL(dev_priv))
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vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |=
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GEN8_PORT_DP_A_HOTPLUG;
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else
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vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
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}
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}
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static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
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{
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struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
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kfree(port->edid);
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port->edid = NULL;
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kfree(port->dpcd);
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port->dpcd = NULL;
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}
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static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
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int type)
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{
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struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
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port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
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if (!port->edid)
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return -ENOMEM;
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port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
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if (!port->dpcd) {
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kfree(port->edid);
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return -ENOMEM;
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}
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memcpy(port->edid->edid_block, virtual_dp_monitor_edid,
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EDID_SIZE);
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port->edid->data_valid = true;
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memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
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port->dpcd->data_valid = true;
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port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
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port->type = type;
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emulate_monitor_status_change(vgpu);
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return 0;
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}
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/**
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* intel_gvt_check_vblank_emulation - check if vblank emulation timer should
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* be turned on/off when a virtual pipe is enabled/disabled.
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* @gvt: a GVT device
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*
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* This function is used to turn on/off vblank timer according to currently
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* enabled/disabled virtual pipes.
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*
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*/
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void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
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{
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struct intel_gvt_irq *irq = &gvt->irq;
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struct intel_vgpu *vgpu;
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bool have_enabled_pipe = false;
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int pipe, id;
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if (WARN_ON(!mutex_is_locked(&gvt->lock)))
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return;
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hrtimer_cancel(&irq->vblank_timer.timer);
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for_each_active_vgpu(gvt, vgpu, id) {
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for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
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have_enabled_pipe =
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pipe_is_enabled(vgpu, pipe);
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if (have_enabled_pipe)
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break;
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}
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}
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if (have_enabled_pipe)
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hrtimer_start(&irq->vblank_timer.timer,
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ktime_add_ns(ktime_get(), irq->vblank_timer.period),
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HRTIMER_MODE_ABS);
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}
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static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct intel_vgpu_irq *irq = &vgpu->irq;
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int vblank_event[] = {
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[PIPE_A] = PIPE_A_VBLANK,
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[PIPE_B] = PIPE_B_VBLANK,
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[PIPE_C] = PIPE_C_VBLANK,
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};
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int event;
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if (pipe < PIPE_A || pipe > PIPE_C)
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return;
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for_each_set_bit(event, irq->flip_done_event[pipe],
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INTEL_GVT_EVENT_MAX) {
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clear_bit(event, irq->flip_done_event[pipe]);
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if (!pipe_is_enabled(vgpu, pipe))
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continue;
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vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
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intel_vgpu_trigger_virtual_event(vgpu, event);
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}
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if (pipe_is_enabled(vgpu, pipe)) {
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vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
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intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
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}
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}
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static void emulate_vblank(struct intel_vgpu *vgpu)
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{
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int pipe;
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for_each_pipe(vgpu->gvt->dev_priv, pipe)
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emulate_vblank_on_pipe(vgpu, pipe);
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}
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/**
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* intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
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* @gvt: a GVT device
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*
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* This function is used to trigger vblank interrupts for vGPUs on GVT device
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*
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*/
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void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
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{
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struct intel_vgpu *vgpu;
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int id;
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if (WARN_ON(!mutex_is_locked(&gvt->lock)))
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return;
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for_each_active_vgpu(gvt, vgpu, id)
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emulate_vblank(vgpu);
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}
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/**
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* intel_vgpu_clean_display - clean vGPU virtual display emulation
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* @vgpu: a vGPU
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*
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* This function is used to clean vGPU virtual display emulation stuffs
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*
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*/
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void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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if (IS_SKYLAKE(dev_priv))
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clean_virtual_dp_monitor(vgpu, PORT_D);
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else
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clean_virtual_dp_monitor(vgpu, PORT_B);
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}
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/**
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* intel_vgpu_init_display- initialize vGPU virtual display emulation
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* @vgpu: a vGPU
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*
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* This function is used to initialize vGPU virtual display emulation stuffs
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*
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* Returns:
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* Zero on success, negative error code if failed.
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*
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*/
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int intel_vgpu_init_display(struct intel_vgpu *vgpu)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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intel_vgpu_init_i2c_edid(vgpu);
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if (IS_SKYLAKE(dev_priv))
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return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D);
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else
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return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B);
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}
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/**
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* intel_vgpu_reset_display- reset vGPU virtual display emulation
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* @vgpu: a vGPU
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*
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* This function is used to reset vGPU virtual display emulation stuffs
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*
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*/
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void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
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{
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emulate_monitor_status_change(vgpu);
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}
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