616 lines
17 KiB
C
616 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for the Texas Instruments DP83867 PHY
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*
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* Copyright (C) 2015 Texas Instruments Inc.
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*/
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#include <linux/ethtool.h>
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#define DP83867_PHY_ID 0x2000a231
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#define DP83867_DEVADDR 0x1f
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#define MII_DP83867_PHYCTRL 0x10
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#define MII_DP83867_MICR 0x12
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#define MII_DP83867_ISR 0x13
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#define DP83867_CFG2 0x14
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#define DP83867_CFG3 0x1e
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#define DP83867_CTRL 0x1f
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/* Extended Registers */
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#define DP83867_CFG4 0x0031
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#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
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#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
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#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
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#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
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#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
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#define DP83867_RGMIICTL 0x0032
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#define DP83867_STRAP_STS1 0x006E
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#define DP83867_STRAP_STS2 0x006f
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#define DP83867_RGMIIDCTL 0x0086
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#define DP83867_RXFCFG 0x0134
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#define DP83867_RXFPMD1 0x0136
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#define DP83867_RXFPMD2 0x0137
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#define DP83867_RXFPMD3 0x0138
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#define DP83867_RXFSOP1 0x0139
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#define DP83867_RXFSOP2 0x013A
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#define DP83867_RXFSOP3 0x013B
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#define DP83867_IO_MUX_CFG 0x0170
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#define DP83867_SGMIICTL 0x00D3
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#define DP83867_10M_SGMII_CFG 0x016F
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#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
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#define DP83867_SW_RESET BIT(15)
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#define DP83867_SW_RESTART BIT(14)
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/* MICR Interrupt bits */
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#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
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#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
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#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
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#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
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#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
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#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
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#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
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#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
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#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
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#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
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#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
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#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
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/* RGMIICTL bits */
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#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
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#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
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/* SGMIICTL bits */
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#define DP83867_SGMII_TYPE BIT(14)
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/* RXFCFG bits*/
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#define DP83867_WOL_MAGIC_EN BIT(0)
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#define DP83867_WOL_BCAST_EN BIT(2)
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#define DP83867_WOL_UCAST_EN BIT(4)
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#define DP83867_WOL_SEC_EN BIT(5)
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#define DP83867_WOL_ENH_MAC BIT(7)
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/* STRAP_STS1 bits */
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#define DP83867_STRAP_STS1_RESERVED BIT(11)
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/* STRAP_STS2 bits */
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#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
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#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
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#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
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#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
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#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
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/* PHY CTRL bits */
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#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
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#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
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#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
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#define DP83867_PHYCR_RESERVED_MASK BIT(11)
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/* RGMIIDCTL bits */
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#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
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#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
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#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
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#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
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/* IO_MUX_CFG bits */
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
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#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
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#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
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#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
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#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
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/* CFG3 bits */
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#define DP83867_CFG3_INT_OE BIT(7)
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#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
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/* CFG4 bits */
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#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
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enum {
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DP83867_PORT_MIRROING_KEEP,
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DP83867_PORT_MIRROING_EN,
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DP83867_PORT_MIRROING_DIS,
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};
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struct dp83867_private {
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u32 rx_id_delay;
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u32 tx_id_delay;
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u32 fifo_depth;
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int io_impedance;
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int port_mirroring;
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bool rxctrl_strap_quirk;
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bool set_clk_output;
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u32 clk_output_sel;
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bool sgmii_ref_clk_en;
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};
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static int dp83867_ack_interrupt(struct phy_device *phydev)
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{
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int err = phy_read(phydev, MII_DP83867_ISR);
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if (err < 0)
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return err;
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return 0;
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}
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static int dp83867_set_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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struct net_device *ndev = phydev->attached_dev;
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u16 val_rxcfg, val_micr;
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u8 *mac;
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val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
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val_micr = phy_read(phydev, MII_DP83867_MICR);
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if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
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WAKE_BCAST)) {
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val_rxcfg |= DP83867_WOL_ENH_MAC;
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val_micr |= MII_DP83867_MICR_WOL_INT_EN;
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if (wol->wolopts & WAKE_MAGIC) {
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mac = (u8 *)ndev->dev_addr;
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if (!is_valid_ether_addr(mac))
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return -EINVAL;
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
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(mac[1] << 8 | mac[0]));
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
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(mac[3] << 8 | mac[2]));
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
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(mac[5] << 8 | mac[4]));
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val_rxcfg |= DP83867_WOL_MAGIC_EN;
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} else {
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val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
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}
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if (wol->wolopts & WAKE_MAGICSECURE) {
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
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(wol->sopass[1] << 8) | wol->sopass[0]);
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
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(wol->sopass[3] << 8) | wol->sopass[2]);
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
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(wol->sopass[5] << 8) | wol->sopass[4]);
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val_rxcfg |= DP83867_WOL_SEC_EN;
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} else {
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val_rxcfg &= ~DP83867_WOL_SEC_EN;
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}
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if (wol->wolopts & WAKE_UCAST)
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val_rxcfg |= DP83867_WOL_UCAST_EN;
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else
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val_rxcfg &= ~DP83867_WOL_UCAST_EN;
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if (wol->wolopts & WAKE_BCAST)
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val_rxcfg |= DP83867_WOL_BCAST_EN;
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else
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val_rxcfg &= ~DP83867_WOL_BCAST_EN;
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} else {
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val_rxcfg &= ~DP83867_WOL_ENH_MAC;
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val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
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}
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
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phy_write(phydev, MII_DP83867_MICR, val_micr);
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return 0;
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}
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static void dp83867_get_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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u16 value, sopass_val;
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wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
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WAKE_MAGICSECURE);
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wol->wolopts = 0;
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value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
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if (value & DP83867_WOL_UCAST_EN)
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wol->wolopts |= WAKE_UCAST;
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if (value & DP83867_WOL_BCAST_EN)
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wol->wolopts |= WAKE_BCAST;
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if (value & DP83867_WOL_MAGIC_EN)
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wol->wolopts |= WAKE_MAGIC;
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if (value & DP83867_WOL_SEC_EN) {
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sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
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DP83867_RXFSOP1);
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wol->sopass[0] = (sopass_val & 0xff);
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wol->sopass[1] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
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DP83867_RXFSOP2);
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wol->sopass[2] = (sopass_val & 0xff);
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wol->sopass[3] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
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DP83867_RXFSOP3);
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wol->sopass[4] = (sopass_val & 0xff);
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wol->sopass[5] = (sopass_val >> 8);
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wol->wolopts |= WAKE_MAGICSECURE;
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}
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if (!(value & DP83867_WOL_ENH_MAC))
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wol->wolopts = 0;
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}
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static int dp83867_config_intr(struct phy_device *phydev)
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{
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int micr_status;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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micr_status = phy_read(phydev, MII_DP83867_MICR);
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if (micr_status < 0)
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return micr_status;
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micr_status |=
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(MII_DP83867_MICR_AN_ERR_INT_EN |
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MII_DP83867_MICR_SPEED_CHNG_INT_EN |
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MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
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MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
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MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
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MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
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return phy_write(phydev, MII_DP83867_MICR, micr_status);
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}
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micr_status = 0x0;
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return phy_write(phydev, MII_DP83867_MICR, micr_status);
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}
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static int dp83867_config_port_mirroring(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867 =
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(struct dp83867_private *)phydev->priv;
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if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
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phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
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DP83867_CFG4_PORT_MIRROR_EN);
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else
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phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
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DP83867_CFG4_PORT_MIRROR_EN);
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return 0;
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}
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#ifdef CONFIG_OF_MDIO
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static int dp83867_of_init(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867 = phydev->priv;
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struct device *dev = &phydev->mdio.dev;
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struct device_node *of_node = dev->of_node;
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int ret;
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if (!of_node)
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return -ENODEV;
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/* Optional configuration */
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ret = of_property_read_u32(of_node, "ti,clk-output-sel",
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&dp83867->clk_output_sel);
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/* If not set, keep default */
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if (!ret) {
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dp83867->set_clk_output = true;
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/* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
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* DP83867_CLK_O_SEL_OFF.
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*/
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if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
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dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
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phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
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dp83867->clk_output_sel);
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return -EINVAL;
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}
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}
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if (of_property_read_bool(of_node, "ti,max-output-impedance"))
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dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
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else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
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dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
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else
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dp83867->io_impedance = -1; /* leave at default */
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dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
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"ti,dp83867-rxctrl-strap-quirk");
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dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
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"ti,sgmii-ref-clock-output-enable");
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/* Existing behavior was to use default pin strapping delay in rgmii
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* mode, but rgmii should have meant no delay. Warn existing users.
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*/
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
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const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
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const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
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DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
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const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
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DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
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if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
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rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
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phydev_warn(phydev,
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"PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
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"Should be 'rgmii-id' to use internal delays\n");
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}
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/* RX delay *must* be specified if internal delay of RX is used. */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
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&dp83867->rx_id_delay);
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if (ret) {
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phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
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return ret;
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}
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if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
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phydev_err(phydev,
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"ti,rx-internal-delay value of %u out of range\n",
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dp83867->rx_id_delay);
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return -EINVAL;
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}
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}
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/* TX delay *must* be specified if internal delay of RX is used. */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
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&dp83867->tx_id_delay);
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if (ret) {
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phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
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return ret;
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}
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if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
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phydev_err(phydev,
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"ti,tx-internal-delay value of %u out of range\n",
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dp83867->tx_id_delay);
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return -EINVAL;
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}
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}
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if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
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dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
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if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
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dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
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ret = of_property_read_u32(of_node, "ti,fifo-depth",
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&dp83867->fifo_depth);
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if (ret) {
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phydev_err(phydev,
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"ti,fifo-depth property is required\n");
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return ret;
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}
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if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
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phydev_err(phydev,
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"ti,fifo-depth value %u out of range\n",
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dp83867->fifo_depth);
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return -EINVAL;
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}
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return 0;
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}
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#else
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static int dp83867_of_init(struct phy_device *phydev)
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{
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return 0;
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}
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#endif /* CONFIG_OF_MDIO */
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static int dp83867_probe(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867;
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dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
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GFP_KERNEL);
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if (!dp83867)
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return -ENOMEM;
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phydev->priv = dp83867;
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return dp83867_of_init(phydev);
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}
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static int dp83867_config_init(struct phy_device *phydev)
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{
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struct dp83867_private *dp83867 = phydev->priv;
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int ret, val, bs;
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u16 delay;
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/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
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if (dp83867->rxctrl_strap_quirk)
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phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
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BIT(7));
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if (phy_interface_is_rgmii(phydev)) {
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val = phy_read(phydev, MII_DP83867_PHYCTRL);
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if (val < 0)
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return val;
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val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
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val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
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/* The code below checks if "port mirroring" N/A MODE4 has been
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* enabled during power on bootstrap.
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*
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* Such N/A mode enabled by mistake can put PHY IC in some
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* internal testing mode and disable RGMII transmission.
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*
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* In this particular case one needs to check STRAP_STS1
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* register's bit 11 (marked as RESERVED).
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*/
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bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
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if (bs & DP83867_STRAP_STS1_RESERVED)
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val &= ~DP83867_PHYCR_RESERVED_MASK;
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ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
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if (ret)
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return ret;
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/* If rgmii mode with no internal delay is selected, we do NOT use
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* aligned mode as one might expect. Instead we use the PHY's default
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* based on pin strapping. And the "mode 0" default is to *use*
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* internal delay with a value of 7 (2.00 ns).
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*
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* Set up RGMII delays
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*/
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val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
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val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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val |= DP83867_RGMII_TX_CLK_DELAY_EN;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
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val |= DP83867_RGMII_RX_CLK_DELAY_EN;
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
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delay = (dp83867->rx_id_delay |
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(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
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delay);
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}
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/* If specified, set io impedance */
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if (dp83867->io_impedance >= 0)
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phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
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DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
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dp83867->io_impedance);
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if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
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/* For support SPEED_10 in SGMII mode
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* DP83867_10M_SGMII_RATE_ADAPT bit
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* has to be cleared by software. That
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* does not affect SPEED_100 and
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* SPEED_1000.
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*/
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ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
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DP83867_10M_SGMII_CFG,
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DP83867_10M_SGMII_RATE_ADAPT_MASK,
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0);
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if (ret)
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return ret;
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/* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
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* are 01). That is not enough to finalize autoneg on some
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* devices. Increase this timer duration to maximum 16ms.
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*/
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ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
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DP83867_CFG4,
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DP83867_CFG4_SGMII_ANEG_MASK,
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DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
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if (ret)
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return ret;
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val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
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/* SGMII type is set to 4-wire mode by default.
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* If we place appropriate property in dts (see above)
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* switch on 6-wire mode.
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*/
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if (dp83867->sgmii_ref_clk_en)
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val |= DP83867_SGMII_TYPE;
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else
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val &= ~DP83867_SGMII_TYPE;
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
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}
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val = phy_read(phydev, DP83867_CFG3);
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/* Enable Interrupt output INT_OE in CFG3 register */
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if (phy_interrupt_is_valid(phydev))
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val |= DP83867_CFG3_INT_OE;
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val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
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phy_write(phydev, DP83867_CFG3, val);
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if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
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dp83867_config_port_mirroring(phydev);
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/* Clock output selection if muxing property is set */
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if (dp83867->set_clk_output) {
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u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
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if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
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val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
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} else {
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mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
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val = dp83867->clk_output_sel <<
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DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
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}
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phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
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mask, val);
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}
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return 0;
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}
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static int dp83867_phy_reset(struct phy_device *phydev)
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{
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int err;
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err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
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if (err < 0)
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return err;
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usleep_range(10, 20);
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return 0;
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}
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static struct phy_driver dp83867_driver[] = {
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{
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.phy_id = DP83867_PHY_ID,
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.phy_id_mask = 0xfffffff0,
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.name = "TI DP83867",
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/* PHY_GBIT_FEATURES */
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.probe = dp83867_probe,
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.config_init = dp83867_config_init,
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.soft_reset = dp83867_phy_reset,
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.get_wol = dp83867_get_wol,
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.set_wol = dp83867_set_wol,
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/* IRQ related */
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.ack_interrupt = dp83867_ack_interrupt,
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.config_intr = dp83867_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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},
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};
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module_phy_driver(dp83867_driver);
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static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
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{ DP83867_PHY_ID, 0xfffffff0 },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
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MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
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MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
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MODULE_LICENSE("GPL v2");
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