131 lines
2.8 KiB
C
131 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/sh/kernel/cpu/sh4a/ubc.c
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*
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* On-chip UBC support for SH-4A CPUs.
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*
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* Copyright (C) 2009 - 2010 Paul Mundt
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*/
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/hw_breakpoint.h>
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#define UBC_CBR(idx) (0xff200000 + (0x20 * idx))
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#define UBC_CRR(idx) (0xff200004 + (0x20 * idx))
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#define UBC_CAR(idx) (0xff200008 + (0x20 * idx))
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#define UBC_CAMR(idx) (0xff20000c + (0x20 * idx))
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#define UBC_CCMFR 0xff200600
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#define UBC_CBCR 0xff200620
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/* CRR */
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#define UBC_CRR_PCB (1 << 1)
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#define UBC_CRR_BIE (1 << 0)
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/* CBR */
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#define UBC_CBR_CE (1 << 0)
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static struct sh_ubc sh4a_ubc;
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static void sh4a_ubc_enable(struct arch_hw_breakpoint *info, int idx)
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{
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__raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx));
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__raw_writel(info->address, UBC_CAR(idx));
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}
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static void sh4a_ubc_disable(struct arch_hw_breakpoint *info, int idx)
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{
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__raw_writel(0, UBC_CBR(idx));
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__raw_writel(0, UBC_CAR(idx));
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}
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static void sh4a_ubc_enable_all(unsigned long mask)
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{
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int i;
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for (i = 0; i < sh4a_ubc.num_events; i++)
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if (mask & (1 << i))
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__raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE,
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UBC_CBR(i));
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}
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static void sh4a_ubc_disable_all(void)
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{
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int i;
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for (i = 0; i < sh4a_ubc.num_events; i++)
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__raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE,
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UBC_CBR(i));
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}
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static unsigned long sh4a_ubc_active_mask(void)
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{
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unsigned long active = 0;
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int i;
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for (i = 0; i < sh4a_ubc.num_events; i++)
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if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE)
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active |= (1 << i);
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return active;
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}
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static unsigned long sh4a_ubc_triggered_mask(void)
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{
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return __raw_readl(UBC_CCMFR);
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}
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static void sh4a_ubc_clear_triggered_mask(unsigned long mask)
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{
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__raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR);
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}
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static struct sh_ubc sh4a_ubc = {
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.name = "SH-4A",
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.num_events = 2,
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.trap_nr = 0x1e0,
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.enable = sh4a_ubc_enable,
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.disable = sh4a_ubc_disable,
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.enable_all = sh4a_ubc_enable_all,
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.disable_all = sh4a_ubc_disable_all,
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.active_mask = sh4a_ubc_active_mask,
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.triggered_mask = sh4a_ubc_triggered_mask,
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.clear_triggered_mask = sh4a_ubc_clear_triggered_mask,
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};
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static int __init sh4a_ubc_init(void)
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{
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struct clk *ubc_iclk = clk_get(NULL, "ubc0");
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int i;
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/*
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* The UBC MSTP bit is optional, as not all platforms will have
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* it. Just ignore it if we can't find it.
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*/
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if (IS_ERR(ubc_iclk))
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ubc_iclk = NULL;
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clk_enable(ubc_iclk);
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__raw_writel(0, UBC_CBCR);
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for (i = 0; i < sh4a_ubc.num_events; i++) {
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__raw_writel(0, UBC_CAMR(i));
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__raw_writel(0, UBC_CBR(i));
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__raw_writel(UBC_CRR_BIE | UBC_CRR_PCB, UBC_CRR(i));
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/* dummy read for write posting */
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(void)__raw_readl(UBC_CRR(i));
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}
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clk_disable(ubc_iclk);
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sh4a_ubc.clk = ubc_iclk;
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return register_sh_ubc(&sh4a_ubc);
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}
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arch_initcall(sh4a_ubc_init);
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