618 lines
21 KiB
C
618 lines
21 KiB
C
/*******************************************************************************
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STMMAC Common Header File
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#ifndef __COMMON_H__
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#define __COMMON_H__
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#include <linux/etherdevice.h>
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#include <linux/netdevice.h>
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#include <linux/stmmac.h>
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#include <linux/phy.h>
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#include <linux/module.h>
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#if IS_ENABLED(CONFIG_VLAN_8021Q)
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#define STMMAC_VLAN_TAG_USED
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#include <linux/if_vlan.h>
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#endif
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#include "descs.h"
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#include "mmc.h"
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/* Synopsys Core versions */
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#define DWMAC_CORE_3_40 0x34
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#define DWMAC_CORE_3_50 0x35
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#define DWMAC_CORE_4_00 0x40
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#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
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/* These need to be power of two, and >= 4 */
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#define DMA_TX_SIZE 512
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#define DMA_RX_SIZE 512
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#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
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#undef FRAME_FILTER_DEBUG
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/* #define FRAME_FILTER_DEBUG */
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/* Extra statistic and debug information exposed by ethtool */
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struct stmmac_extra_stats {
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/* Transmit errors */
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unsigned long tx_underflow ____cacheline_aligned;
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unsigned long tx_carrier;
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unsigned long tx_losscarrier;
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unsigned long vlan_tag;
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unsigned long tx_deferred;
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unsigned long tx_vlan;
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unsigned long tx_jabber;
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unsigned long tx_frame_flushed;
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unsigned long tx_payload_error;
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unsigned long tx_ip_header_error;
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/* Receive errors */
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unsigned long rx_desc;
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unsigned long sa_filter_fail;
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unsigned long overflow_error;
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unsigned long ipc_csum_error;
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unsigned long rx_collision;
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unsigned long rx_crc_errors;
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unsigned long dribbling_bit;
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unsigned long rx_length;
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unsigned long rx_mii;
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unsigned long rx_multicast;
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unsigned long rx_gmac_overflow;
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unsigned long rx_watchdog;
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unsigned long da_rx_filter_fail;
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unsigned long sa_rx_filter_fail;
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unsigned long rx_missed_cntr;
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unsigned long rx_overflow_cntr;
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unsigned long rx_vlan;
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/* Tx/Rx IRQ error info */
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unsigned long tx_undeflow_irq;
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unsigned long tx_process_stopped_irq;
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unsigned long tx_jabber_irq;
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unsigned long rx_overflow_irq;
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unsigned long rx_buf_unav_irq;
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unsigned long rx_process_stopped_irq;
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unsigned long rx_watchdog_irq;
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unsigned long tx_early_irq;
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unsigned long fatal_bus_error_irq;
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/* Tx/Rx IRQ Events */
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unsigned long rx_early_irq;
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unsigned long threshold;
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unsigned long tx_pkt_n;
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unsigned long rx_pkt_n;
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unsigned long normal_irq_n;
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unsigned long rx_normal_irq_n;
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unsigned long napi_poll;
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unsigned long tx_normal_irq_n;
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unsigned long tx_clean;
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unsigned long tx_set_ic_bit;
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unsigned long irq_receive_pmt_irq_n;
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/* MMC info */
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unsigned long mmc_tx_irq_n;
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unsigned long mmc_rx_irq_n;
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unsigned long mmc_rx_csum_offload_irq_n;
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/* EEE */
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unsigned long irq_tx_path_in_lpi_mode_n;
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unsigned long irq_tx_path_exit_lpi_mode_n;
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unsigned long irq_rx_path_in_lpi_mode_n;
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unsigned long irq_rx_path_exit_lpi_mode_n;
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unsigned long phy_eee_wakeup_error_n;
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/* Extended RDES status */
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unsigned long ip_hdr_err;
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unsigned long ip_payload_err;
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unsigned long ip_csum_bypassed;
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unsigned long ipv4_pkt_rcvd;
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unsigned long ipv6_pkt_rcvd;
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unsigned long no_ptp_rx_msg_type_ext;
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unsigned long ptp_rx_msg_type_sync;
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unsigned long ptp_rx_msg_type_follow_up;
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unsigned long ptp_rx_msg_type_delay_req;
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unsigned long ptp_rx_msg_type_delay_resp;
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unsigned long ptp_rx_msg_type_pdelay_req;
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unsigned long ptp_rx_msg_type_pdelay_resp;
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unsigned long ptp_rx_msg_type_pdelay_follow_up;
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unsigned long ptp_rx_msg_type_announce;
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unsigned long ptp_rx_msg_type_management;
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unsigned long ptp_rx_msg_pkt_reserved_type;
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unsigned long ptp_frame_type;
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unsigned long ptp_ver;
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unsigned long timestamp_dropped;
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unsigned long av_pkt_rcvd;
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unsigned long av_tagged_pkt_rcvd;
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unsigned long vlan_tag_priority_val;
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unsigned long l3_filter_match;
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unsigned long l4_filter_match;
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unsigned long l3_l4_filter_no_match;
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/* PCS */
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unsigned long irq_pcs_ane_n;
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unsigned long irq_pcs_link_n;
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unsigned long irq_rgmii_n;
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unsigned long pcs_link;
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unsigned long pcs_duplex;
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unsigned long pcs_speed;
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/* debug register */
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unsigned long mtl_tx_status_fifo_full;
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unsigned long mtl_tx_fifo_not_empty;
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unsigned long mmtl_fifo_ctrl;
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unsigned long mtl_tx_fifo_read_ctrl_write;
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unsigned long mtl_tx_fifo_read_ctrl_wait;
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unsigned long mtl_tx_fifo_read_ctrl_read;
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unsigned long mtl_tx_fifo_read_ctrl_idle;
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unsigned long mac_tx_in_pause;
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unsigned long mac_tx_frame_ctrl_xfer;
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unsigned long mac_tx_frame_ctrl_idle;
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unsigned long mac_tx_frame_ctrl_wait;
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unsigned long mac_tx_frame_ctrl_pause;
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unsigned long mac_gmii_tx_proto_engine;
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unsigned long mtl_rx_fifo_fill_level_full;
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unsigned long mtl_rx_fifo_fill_above_thresh;
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unsigned long mtl_rx_fifo_fill_below_thresh;
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unsigned long mtl_rx_fifo_fill_level_empty;
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unsigned long mtl_rx_fifo_read_ctrl_flush;
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unsigned long mtl_rx_fifo_read_ctrl_read_data;
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unsigned long mtl_rx_fifo_read_ctrl_status;
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unsigned long mtl_rx_fifo_read_ctrl_idle;
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unsigned long mtl_rx_fifo_ctrl_active;
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unsigned long mac_rx_frame_ctrl_fifo;
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unsigned long mac_gmii_rx_proto_engine;
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/* TSO */
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unsigned long tx_tso_frames;
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unsigned long tx_tso_nfrags;
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};
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/* CSR Frequency Access Defines*/
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#define CSR_F_35M 35000000
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#define CSR_F_60M 60000000
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#define CSR_F_100M 100000000
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#define CSR_F_150M 150000000
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#define CSR_F_250M 250000000
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#define CSR_F_300M 300000000
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#define MAC_CSR_H_FRQ_MASK 0x20
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#define HASH_TABLE_SIZE 64
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#define PAUSE_TIME 0xffff
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/* Flow Control defines */
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#define FLOW_OFF 0
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#define FLOW_RX 1
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#define FLOW_TX 2
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#define FLOW_AUTO (FLOW_TX | FLOW_RX)
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/* PCS defines */
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#define STMMAC_PCS_RGMII (1 << 0)
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#define STMMAC_PCS_SGMII (1 << 1)
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#define STMMAC_PCS_TBI (1 << 2)
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#define STMMAC_PCS_RTBI (1 << 3)
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#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
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/* DAM HW feature register fields */
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#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
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#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
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#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
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#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
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#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
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#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
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#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
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#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
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#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
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#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
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#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
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#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
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#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
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#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
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#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
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#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
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#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
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#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
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#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
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#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
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#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
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#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
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#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
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/* Timestamping with Internal System Time */
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#define DMA_HW_FEAT_INTTSEN 0x02000000
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#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
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#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
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#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
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#define DEFAULT_DMA_PBL 8
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/* PCS status and mask defines */
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#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
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#define PCS_LINK_IRQ BIT(1) /* PCS Link */
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#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
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/* Max/Min RI Watchdog Timer count value */
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#define MAX_DMA_RIWT 0xff
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#define MIN_DMA_RIWT 0x20
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/* Tx coalesce parameters */
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#define STMMAC_COAL_TX_TIMER 40000
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#define STMMAC_MAX_COAL_TX_TICK 100000
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#define STMMAC_TX_MAX_FRAMES 256
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#define STMMAC_TX_FRAMES 64
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/* Rx IPC status */
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enum rx_frame_status {
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good_frame = 0x0,
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discard_frame = 0x1,
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csum_none = 0x2,
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llc_snap = 0x4,
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dma_own = 0x8,
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rx_not_ls = 0x10,
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};
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/* Tx status */
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enum tx_frame_status {
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tx_done = 0x0,
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tx_not_ls = 0x1,
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tx_err = 0x2,
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tx_dma_own = 0x4,
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};
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enum dma_irq_status {
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tx_hard_error = 0x1,
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tx_hard_error_bump_tc = 0x2,
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handle_rx = 0x4,
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handle_tx = 0x8,
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};
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/* EEE and LPI defines */
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#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
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#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
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#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
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#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
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#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
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/* Physical Coding Sublayer */
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struct rgmii_adv {
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unsigned int pause;
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unsigned int duplex;
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unsigned int lp_pause;
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unsigned int lp_duplex;
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};
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#define STMMAC_PCS_PAUSE 1
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#define STMMAC_PCS_ASYM_PAUSE 2
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/* DMA HW capabilities */
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struct dma_features {
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unsigned int mbps_10_100;
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unsigned int mbps_1000;
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unsigned int half_duplex;
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unsigned int hash_filter;
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unsigned int multi_addr;
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unsigned int pcs;
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unsigned int sma_mdio;
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unsigned int pmt_remote_wake_up;
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unsigned int pmt_magic_frame;
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unsigned int rmon;
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/* IEEE 1588-2002 */
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unsigned int time_stamp;
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/* IEEE 1588-2008 */
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unsigned int atime_stamp;
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/* 802.3az - Energy-Efficient Ethernet (EEE) */
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unsigned int eee;
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unsigned int av;
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unsigned int tsoen;
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/* TX and RX csum */
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unsigned int tx_coe;
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unsigned int rx_coe;
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unsigned int rx_coe_type1;
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unsigned int rx_coe_type2;
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unsigned int rxfifo_over_2048;
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/* TX and RX number of channels */
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unsigned int number_rx_channel;
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unsigned int number_tx_channel;
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/* TX and RX number of queues */
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unsigned int number_rx_queues;
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unsigned int number_tx_queues;
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/* Alternate (enhanced) DESC mode */
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unsigned int enh_desc;
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/* TX and RX FIFO sizes */
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unsigned int tx_fifo_size;
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unsigned int rx_fifo_size;
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};
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/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
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#define BUF_SIZE_16KiB 16384
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#define BUF_SIZE_8KiB 8192
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#define BUF_SIZE_4KiB 4096
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#define BUF_SIZE_2KiB 2048
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/* Power Down and WOL */
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#define PMT_NOT_SUPPORTED 0
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#define PMT_SUPPORTED 1
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/* Common MAC defines */
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#define MAC_CTRL_REG 0x00000000 /* MAC Control */
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#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
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#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
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/* Default LPI timers */
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#define STMMAC_DEFAULT_LIT_LS 0x3E8
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#define STMMAC_DEFAULT_TWT_LS 0x1E
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#define STMMAC_CHAIN_MODE 0x1
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#define STMMAC_RING_MODE 0x2
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#define JUMBO_LEN 9000
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/* Descriptors helpers */
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struct stmmac_desc_ops {
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/* DMA RX descriptor ring initialization */
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void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
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int end);
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/* DMA TX descriptor ring initialization */
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void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
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/* Invoked by the xmit function to prepare the tx descriptor */
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void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
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bool csum_flag, int mode, bool tx_own,
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bool ls);
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void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
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int len2, bool tx_own, bool ls,
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unsigned int tcphdrlen,
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unsigned int tcppayloadlen);
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/* Set/get the owner of the descriptor */
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void (*set_tx_owner) (struct dma_desc *p);
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int (*get_tx_owner) (struct dma_desc *p);
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/* Clean the tx descriptor as soon as the tx irq is received */
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void (*release_tx_desc) (struct dma_desc *p, int mode);
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/* Clear interrupt on tx frame completion. When this bit is
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* set an interrupt happens as soon as the frame is transmitted */
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void (*set_tx_ic)(struct dma_desc *p);
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/* Last tx segment reports the transmit status */
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int (*get_tx_ls) (struct dma_desc *p);
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/* Return the transmit status looking at the TDES1 */
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int (*tx_status) (void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p, void __iomem *ioaddr);
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/* Get the buffer size from the descriptor */
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int (*get_tx_len) (struct dma_desc *p);
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/* Handle extra events on specific interrupts hw dependent */
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void (*set_rx_owner) (struct dma_desc *p);
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/* Get the receive frame size */
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int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
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/* Return the reception status looking at the RDES1 */
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int (*rx_status) (void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p);
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void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
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struct dma_extended_desc *p);
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/* Set tx timestamp enable bit */
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void (*enable_tx_timestamp) (struct dma_desc *p);
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/* get tx timestamp status */
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int (*get_tx_timestamp_status) (struct dma_desc *p);
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/* get timestamp value */
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u64(*get_timestamp) (void *desc, u32 ats);
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/* get rx timestamp status */
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int (*get_rx_timestamp_status) (void *desc, u32 ats);
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/* Display ring */
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void (*display_ring)(void *head, unsigned int size, bool rx);
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/* set MSS via context descriptor */
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void (*set_mss)(struct dma_desc *p, unsigned int mss);
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};
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extern const struct stmmac_desc_ops enh_desc_ops;
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extern const struct stmmac_desc_ops ndesc_ops;
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/* Specific DMA helpers */
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struct stmmac_dma_ops {
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/* DMA core initialization */
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int (*reset)(void __iomem *ioaddr);
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void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx, u32 dma_rx, int atds);
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/* Configure the AXI Bus Mode Register */
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void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
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/* Dump DMA registers */
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void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);
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/* Set tx/rx threshold in the csr6 register
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* An invalid value enables the store-and-forward mode */
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void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
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int rxfifosz);
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void (*dma_rx_mode)(void __iomem *ioaddr, int mode, u32 channel,
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int fifosz);
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void (*dma_tx_mode)(void __iomem *ioaddr, int mode, u32 channel);
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/* To track extra statistic (if supported) */
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void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
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void __iomem *ioaddr);
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void (*enable_dma_transmission) (void __iomem *ioaddr);
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void (*enable_dma_irq)(void __iomem *ioaddr, u32 chan);
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void (*disable_dma_irq)(void __iomem *ioaddr, u32 chan);
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void (*start_tx)(void __iomem *ioaddr, u32 chan);
|
|
void (*stop_tx)(void __iomem *ioaddr, u32 chan);
|
|
void (*start_rx)(void __iomem *ioaddr, u32 chan);
|
|
void (*stop_rx)(void __iomem *ioaddr, u32 chan);
|
|
int (*dma_interrupt) (void __iomem *ioaddr,
|
|
struct stmmac_extra_stats *x);
|
|
/* If supported then get the optional core features */
|
|
void (*get_hw_feature)(void __iomem *ioaddr,
|
|
struct dma_features *dma_cap);
|
|
/* Program the HW RX Watchdog */
|
|
void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
|
|
void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len);
|
|
void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len);
|
|
void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
|
|
void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
|
|
void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
|
|
};
|
|
|
|
struct mac_device_info;
|
|
|
|
/* Helpers to program the MAC core */
|
|
struct stmmac_ops {
|
|
/* MAC core initialization */
|
|
void (*core_init)(struct mac_device_info *hw, int mtu);
|
|
/* Enable and verify that the IPC module is supported */
|
|
int (*rx_ipc)(struct mac_device_info *hw);
|
|
/* Enable RX Queues */
|
|
void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);
|
|
/* Program RX Algorithms */
|
|
void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
|
|
/* Program TX Algorithms */
|
|
void (*prog_mtl_tx_algorithms)(struct mac_device_info *hw, u32 tx_alg);
|
|
/* Set MTL TX queues weight */
|
|
void (*set_mtl_tx_queue_weight)(struct mac_device_info *hw,
|
|
u32 weight, u32 queue);
|
|
/* RX MTL queue to RX dma mapping */
|
|
void (*map_mtl_to_dma)(struct mac_device_info *hw, u32 queue, u32 chan);
|
|
/* Configure AV Algorithm */
|
|
void (*config_cbs)(struct mac_device_info *hw, u32 send_slope,
|
|
u32 idle_slope, u32 high_credit, u32 low_credit,
|
|
u32 queue);
|
|
/* Dump MAC registers */
|
|
void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
|
|
/* Handle extra events on specific interrupts hw dependent */
|
|
int (*host_irq_status)(struct mac_device_info *hw,
|
|
struct stmmac_extra_stats *x);
|
|
/* Handle MTL interrupts */
|
|
int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);
|
|
/* Multicast filter setting */
|
|
void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
|
|
/* Flow control setting */
|
|
void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
|
|
unsigned int fc, unsigned int pause_time, u32 tx_cnt);
|
|
/* Set power management mode (e.g. magic frame) */
|
|
void (*pmt)(struct mac_device_info *hw, unsigned long mode);
|
|
/* Set/Get Unicast MAC addresses */
|
|
void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
|
|
unsigned int reg_n);
|
|
void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
|
|
unsigned int reg_n);
|
|
void (*set_eee_mode)(struct mac_device_info *hw,
|
|
bool en_tx_lpi_clockgating);
|
|
void (*reset_eee_mode)(struct mac_device_info *hw);
|
|
void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
|
|
void (*set_eee_pls)(struct mac_device_info *hw, int link);
|
|
void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x,
|
|
u32 rx_queues, u32 tx_queues);
|
|
/* PCS calls */
|
|
void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
|
|
bool loopback);
|
|
void (*pcs_rane)(void __iomem *ioaddr, bool restart);
|
|
void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
|
|
};
|
|
|
|
/* PTP and HW Timer helpers */
|
|
struct stmmac_hwtimestamp {
|
|
void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
|
|
u32 (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,
|
|
int gmac4);
|
|
int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
|
|
int (*config_addend) (void __iomem *ioaddr, u32 addend);
|
|
int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
|
|
int add_sub, int gmac4);
|
|
u64(*get_systime) (void __iomem *ioaddr);
|
|
};
|
|
|
|
extern const struct stmmac_hwtimestamp stmmac_ptp;
|
|
extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
|
|
|
|
struct mac_link {
|
|
int port;
|
|
int duplex;
|
|
int speed;
|
|
};
|
|
|
|
struct mii_regs {
|
|
unsigned int addr; /* MII Address */
|
|
unsigned int data; /* MII Data */
|
|
unsigned int addr_shift; /* MII address shift */
|
|
unsigned int reg_shift; /* MII reg shift */
|
|
unsigned int addr_mask; /* MII address mask */
|
|
unsigned int reg_mask; /* MII reg mask */
|
|
unsigned int clk_csr_shift;
|
|
unsigned int clk_csr_mask;
|
|
};
|
|
|
|
/* Helpers to manage the descriptors for chain and ring modes */
|
|
struct stmmac_mode_ops {
|
|
void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
|
|
unsigned int extend_desc);
|
|
unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
|
|
int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
|
|
int (*set_16kib_bfsize)(int mtu);
|
|
void (*init_desc3)(struct dma_desc *p);
|
|
void (*refill_desc3) (void *priv, struct dma_desc *p);
|
|
void (*clean_desc3) (void *priv, struct dma_desc *p);
|
|
};
|
|
|
|
struct mac_device_info {
|
|
const struct stmmac_ops *mac;
|
|
const struct stmmac_desc_ops *desc;
|
|
const struct stmmac_dma_ops *dma;
|
|
const struct stmmac_mode_ops *mode;
|
|
const struct stmmac_hwtimestamp *ptp;
|
|
struct mii_regs mii; /* MII register Addresses */
|
|
struct mac_link link;
|
|
void __iomem *pcsr; /* vpointer to device CSRs */
|
|
int multicast_filter_bins;
|
|
int unicast_filter_entries;
|
|
int mcast_bits_log2;
|
|
unsigned int rx_csum;
|
|
unsigned int pcs;
|
|
unsigned int pmt;
|
|
unsigned int ps;
|
|
};
|
|
|
|
struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
|
|
int perfect_uc_entries,
|
|
int *synopsys_id);
|
|
struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
|
|
struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
|
|
int perfect_uc_entries, int *synopsys_id);
|
|
|
|
void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
|
|
unsigned int high, unsigned int low);
|
|
void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
|
|
unsigned int high, unsigned int low);
|
|
void stmmac_set_mac(void __iomem *ioaddr, bool enable);
|
|
|
|
void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
|
|
unsigned int high, unsigned int low);
|
|
void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
|
|
unsigned int high, unsigned int low);
|
|
void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
|
|
|
|
void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
|
|
|
|
extern const struct stmmac_mode_ops ring_mode_ops;
|
|
extern const struct stmmac_mode_ops chain_mode_ops;
|
|
extern const struct stmmac_desc_ops dwmac4_desc_ops;
|
|
|
|
/**
|
|
* stmmac_get_synopsys_id - return the SYINID.
|
|
* @priv: driver private structure
|
|
* Description: this simple function is to decode and return the SYINID
|
|
* starting from the HW core register.
|
|
*/
|
|
static inline u32 stmmac_get_synopsys_id(u32 hwid)
|
|
{
|
|
/* Check Synopsys Id (not available on old chips) */
|
|
if (likely(hwid)) {
|
|
u32 uid = ((hwid & 0x0000ff00) >> 8);
|
|
u32 synid = (hwid & 0x000000ff);
|
|
|
|
pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
|
|
uid, synid);
|
|
|
|
return synid;
|
|
}
|
|
return 0;
|
|
}
|
|
#endif /* __COMMON_H__ */
|