572 lines
15 KiB
C
572 lines
15 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#include "iwl-dev.h"
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#include "iwl-trans.h"
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#include "iwl-core.h"
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#include "iwl-helpers.h"
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/*TODO remove uneeded includes when the transport layer tx_free will be here */
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#include "iwl-agn.h"
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#include "iwl-core.h"
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static int iwl_trans_rx_alloc(struct iwl_priv *priv)
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{
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struct iwl_rx_queue *rxq = &priv->rxq;
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struct device *dev = priv->bus.dev;
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memset(&priv->rxq, 0, sizeof(priv->rxq));
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spin_lock_init(&rxq->lock);
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INIT_LIST_HEAD(&rxq->rx_free);
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INIT_LIST_HEAD(&rxq->rx_used);
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if (WARN_ON(rxq->bd || rxq->rb_stts))
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return -EINVAL;
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/* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
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rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
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&rxq->bd_dma, GFP_KERNEL);
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if (!rxq->bd)
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goto err_bd;
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memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
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/*Allocate the driver's pointer to receive buffer status */
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rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
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&rxq->rb_stts_dma, GFP_KERNEL);
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if (!rxq->rb_stts)
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goto err_rb_stts;
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memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
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return 0;
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err_rb_stts:
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dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
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rxq->bd, rxq->bd_dma);
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memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
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rxq->bd = NULL;
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err_bd:
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return -ENOMEM;
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}
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static void iwl_trans_rxq_free_rx_bufs(struct iwl_priv *priv)
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{
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struct iwl_rx_queue *rxq = &priv->rxq;
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int i;
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/* Fill the rx_used queue with _all_ of the Rx buffers */
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for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
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/* In the reset function, these buffers may have been allocated
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* to an SKB, so we need to unmap and free potential storage */
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if (rxq->pool[i].page != NULL) {
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dma_unmap_page(priv->bus.dev, rxq->pool[i].page_dma,
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PAGE_SIZE << priv->hw_params.rx_page_order,
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DMA_FROM_DEVICE);
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__iwl_free_pages(priv, rxq->pool[i].page);
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rxq->pool[i].page = NULL;
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}
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list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
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}
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}
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static int iwl_trans_rx_init(struct iwl_priv *priv)
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{
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struct iwl_rx_queue *rxq = &priv->rxq;
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int i, err;
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unsigned long flags;
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if (!rxq->bd) {
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err = iwl_trans_rx_alloc(priv);
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if (err)
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return err;
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}
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spin_lock_irqsave(&rxq->lock, flags);
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INIT_LIST_HEAD(&rxq->rx_free);
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INIT_LIST_HEAD(&rxq->rx_used);
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iwl_trans_rxq_free_rx_bufs(priv);
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for (i = 0; i < RX_QUEUE_SIZE; i++)
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rxq->queue[i] = NULL;
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/* Set us so that we have processed and used all buffers, but have
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* not restocked the Rx queue with fresh buffers */
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rxq->read = rxq->write = 0;
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rxq->write_actual = 0;
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rxq->free_count = 0;
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spin_unlock_irqrestore(&rxq->lock, flags);
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return 0;
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}
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static void iwl_trans_rx_free(struct iwl_priv *priv)
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{
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struct iwl_rx_queue *rxq = &priv->rxq;
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unsigned long flags;
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/*if rxq->bd is NULL, it means that nothing has been allocated,
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* exit now */
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if (!rxq->bd) {
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IWL_DEBUG_INFO(priv, "Free NULL rx context\n");
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return;
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}
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spin_lock_irqsave(&rxq->lock, flags);
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iwl_trans_rxq_free_rx_bufs(priv);
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spin_unlock_irqrestore(&rxq->lock, flags);
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dma_free_coherent(priv->bus.dev, sizeof(__le32) * RX_QUEUE_SIZE,
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rxq->bd, rxq->bd_dma);
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memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
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rxq->bd = NULL;
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if (rxq->rb_stts)
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dma_free_coherent(priv->bus.dev,
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sizeof(struct iwl_rb_status),
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rxq->rb_stts, rxq->rb_stts_dma);
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else
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IWL_DEBUG_INFO(priv, "Free rxq->rb_stts which is NULL\n");
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memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
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rxq->rb_stts = NULL;
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}
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static int iwl_trans_rx_stop(struct iwl_priv *priv)
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{
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/* stop Rx DMA */
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iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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return iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
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FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
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}
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static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
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struct iwl_dma_ptr *ptr, size_t size)
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{
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if (WARN_ON(ptr->addr))
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return -EINVAL;
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ptr->addr = dma_alloc_coherent(priv->bus.dev, size,
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&ptr->dma, GFP_KERNEL);
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if (!ptr->addr)
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return -ENOMEM;
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ptr->size = size;
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return 0;
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}
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static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
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struct iwl_dma_ptr *ptr)
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{
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if (unlikely(!ptr->addr))
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return;
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dma_free_coherent(priv->bus.dev, ptr->size, ptr->addr, ptr->dma);
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memset(ptr, 0, sizeof(*ptr));
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}
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static int iwl_trans_txq_alloc(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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int slots_num, u32 txq_id)
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{
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size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
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int i;
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if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds))
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return -EINVAL;
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txq->q.n_window = slots_num;
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txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num,
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GFP_KERNEL);
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txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num,
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GFP_KERNEL);
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if (!txq->meta || !txq->cmd)
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goto error;
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for (i = 0; i < slots_num; i++) {
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txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
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GFP_KERNEL);
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if (!txq->cmd[i])
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goto error;
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}
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/* Alloc driver data array and TFD circular buffer */
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/* Driver private data, only for Tx (not command) queues,
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* not shared with device. */
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if (txq_id != priv->cmd_queue) {
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txq->txb = kzalloc(sizeof(txq->txb[0]) *
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TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
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if (!txq->txb) {
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IWL_ERR(priv, "kmalloc for auxiliary BD "
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"structures failed\n");
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goto error;
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}
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} else {
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txq->txb = NULL;
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}
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/* Circular buffer of transmit frame descriptors (TFDs),
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* shared with device */
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txq->tfds = dma_alloc_coherent(priv->bus.dev, tfd_sz, &txq->q.dma_addr,
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GFP_KERNEL);
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if (!txq->tfds) {
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IWL_ERR(priv, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
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goto error;
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}
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txq->q.id = txq_id;
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return 0;
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error:
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kfree(txq->txb);
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txq->txb = NULL;
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/* since txq->cmd has been zeroed,
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* all non allocated cmd[i] will be NULL */
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if (txq->cmd)
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for (i = 0; i < slots_num; i++)
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kfree(txq->cmd[i]);
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kfree(txq->meta);
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kfree(txq->cmd);
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txq->meta = NULL;
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txq->cmd = NULL;
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return -ENOMEM;
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}
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static int iwl_trans_txq_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
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int slots_num, u32 txq_id)
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{
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int ret;
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txq->need_update = 0;
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memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
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/*
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* For the default queues 0-3, set up the swq_id
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* already -- all others need to get one later
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* (if they need one at all).
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*/
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if (txq_id < 4)
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iwl_set_swq_id(txq, txq_id, txq_id);
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/* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
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* iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
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BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
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/* Initialize queue's high/low-water marks, and head/tail indexes */
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ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
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txq_id);
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if (ret)
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return ret;
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/*
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* Tell nic where to find circular buffer of Tx Frame Descriptors for
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* given Tx queue, and enable the DMA channel used for that queue.
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* Circular buffer (TFD queue in DRAM) physical base address */
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iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
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txq->q.dma_addr >> 8);
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return 0;
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}
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/**
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* iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
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*/
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static void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
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{
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struct iwl_tx_queue *txq = &priv->txq[txq_id];
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struct iwl_queue *q = &txq->q;
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if (!q->n_bd)
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return;
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while (q->write_ptr != q->read_ptr) {
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/* The read_ptr needs to bound by q->n_window */
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iwlagn_txq_free_tfd(priv, txq, get_cmd_index(q, q->read_ptr));
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q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
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}
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}
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/**
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* iwl_tx_queue_free - Deallocate DMA queue.
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* @txq: Transmit queue to deallocate.
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*
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* Empty queue by removing and destroying all BD's.
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* Free all buffers.
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* 0-fill, but do not free "txq" descriptor structure.
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*/
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static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
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{
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struct iwl_tx_queue *txq = &priv->txq[txq_id];
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struct device *dev = priv->bus.dev;
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int i;
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if (WARN_ON(!txq))
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return;
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iwl_tx_queue_unmap(priv, txq_id);
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/* De-alloc array of command/tx buffers */
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for (i = 0; i < txq->q.n_window; i++)
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kfree(txq->cmd[i]);
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/* De-alloc circular buffer of TFDs */
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if (txq->q.n_bd) {
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dma_free_coherent(dev, priv->hw_params.tfd_size *
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txq->q.n_bd, txq->tfds, txq->q.dma_addr);
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memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
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}
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/* De-alloc array of per-TFD driver data */
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kfree(txq->txb);
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txq->txb = NULL;
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/* deallocate arrays */
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kfree(txq->cmd);
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kfree(txq->meta);
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txq->cmd = NULL;
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txq->meta = NULL;
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/* 0-fill queue descriptor structure */
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memset(txq, 0, sizeof(*txq));
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}
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/**
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* iwl_trans_tx_free - Free TXQ Context
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*
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* Destroy all TX DMA queues and structures
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*/
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static void iwl_trans_tx_free(struct iwl_priv *priv)
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{
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int txq_id;
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/* Tx queues */
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if (priv->txq) {
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
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iwl_tx_queue_free(priv, txq_id);
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}
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kfree(priv->txq);
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priv->txq = NULL;
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iwlagn_free_dma_ptr(priv, &priv->kw);
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iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
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}
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/**
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* iwl_trans_tx_alloc - allocate TX context
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* Allocate all Tx DMA structures and initialize them
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*
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* @param priv
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* @return error code
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*/
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static int iwl_trans_tx_alloc(struct iwl_priv *priv)
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{
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int ret;
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int txq_id, slots_num;
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/*It is not allowed to alloc twice, so warn when this happens.
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* We cannot rely on the previous allocation, so free and fail */
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if (WARN_ON(priv->txq)) {
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ret = -EINVAL;
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goto error;
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}
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ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
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priv->hw_params.scd_bc_tbls_size);
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if (ret) {
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IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
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goto error;
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}
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/* Alloc keep-warm buffer */
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ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
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if (ret) {
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IWL_ERR(priv, "Keep Warm allocation failed\n");
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goto error;
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}
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priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
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priv->cfg->base_params->num_of_queues, GFP_KERNEL);
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if (!priv->txq) {
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IWL_ERR(priv, "Not enough memory for txq\n");
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ret = ENOMEM;
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goto error;
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}
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/* Alloc and init all Tx queues, including the command queue (#4/#9) */
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for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
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slots_num = (txq_id == priv->cmd_queue) ?
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TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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ret = iwl_trans_txq_alloc(priv, &priv->txq[txq_id], slots_num,
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txq_id);
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if (ret) {
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IWL_ERR(priv, "Tx %d queue alloc failed\n", txq_id);
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goto error;
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}
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}
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return 0;
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error:
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trans_tx_free(priv);
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return ret;
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}
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static int iwl_trans_tx_init(struct iwl_priv *priv)
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{
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int ret;
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int txq_id, slots_num;
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unsigned long flags;
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bool alloc = false;
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if (!priv->txq) {
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ret = iwl_trans_tx_alloc(priv);
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if (ret)
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goto error;
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alloc = true;
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}
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|
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spin_lock_irqsave(&priv->lock, flags);
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|
|
/* Turn off all Tx DMA fifos */
|
|
iwl_write_prph(priv, IWLAGN_SCD_TXFACT, 0);
|
|
|
|
/* Tell NIC where to find the "keep warm" buffer */
|
|
iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
/* Alloc and init all Tx queues, including the command queue (#4/#9) */
|
|
for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
|
|
slots_num = (txq_id == priv->cmd_queue) ?
|
|
TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
|
|
ret = iwl_trans_txq_init(priv, &priv->txq[txq_id], slots_num,
|
|
txq_id);
|
|
if (ret) {
|
|
IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
|
|
goto error;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
error:
|
|
/*Upon error, free only if we allocated something */
|
|
if (alloc)
|
|
trans_tx_free(priv);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* iwlagn_txq_ctx_stop - Stop all Tx DMA channels
|
|
*/
|
|
static int iwl_trans_tx_stop(struct iwl_priv *priv)
|
|
{
|
|
int ch, txq_id;
|
|
unsigned long flags;
|
|
|
|
/* Turn off all Tx DMA fifos */
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
iwlagn_txq_set_sched(priv, 0);
|
|
|
|
/* Stop each Tx DMA channel, and wait for it to be idle */
|
|
for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
|
|
iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
|
|
if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
|
|
FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
|
|
1000))
|
|
IWL_ERR(priv, "Failing on timeout while stopping"
|
|
" DMA channel %d [0x%08x]", ch,
|
|
iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
|
|
}
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
if (!priv->txq) {
|
|
IWL_WARN(priv, "Stopping tx queues that aren't allocated...");
|
|
return 0;
|
|
}
|
|
|
|
/* Unmap DMA from host system and free skb's */
|
|
for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
|
|
iwl_tx_queue_unmap(priv, txq_id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct iwl_trans_ops trans_ops = {
|
|
.rx_init = iwl_trans_rx_init,
|
|
.rx_stop = iwl_trans_rx_stop,
|
|
.rx_free = iwl_trans_rx_free,
|
|
|
|
.tx_init = iwl_trans_tx_init,
|
|
.tx_stop = iwl_trans_tx_stop,
|
|
.tx_free = iwl_trans_tx_free,
|
|
|
|
.send_cmd = iwl_send_cmd,
|
|
.send_cmd_pdu = iwl_send_cmd_pdu,
|
|
};
|
|
|
|
void iwl_trans_register(struct iwl_trans *trans)
|
|
{
|
|
trans->ops = &trans_ops;
|
|
}
|