390 lines
9.6 KiB
C
390 lines
9.6 KiB
C
/*
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* This contains the functions to handle the descriptors for DesignWare databook
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* 4.xx.
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*
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* Copyright (C) 2015 STMicroelectronics Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#include <linux/stmmac.h>
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#include "common.h"
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#include "dwmac4_descs.h"
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static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p,
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void __iomem *ioaddr)
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{
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struct net_device_stats *stats = (struct net_device_stats *)data;
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unsigned int tdes3;
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int ret = tx_done;
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tdes3 = p->des3;
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/* Get tx owner first */
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if (unlikely(tdes3 & TDES3_OWN))
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return tx_dma_own;
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/* Verify tx error by looking at the last segment. */
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if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
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return tx_not_ls;
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if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
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if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
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x->tx_jabber++;
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if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
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x->tx_frame_flushed++;
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if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
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x->tx_losscarrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
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x->tx_carrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
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(tdes3 & TDES3_EXCESSIVE_COLLISION)))
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stats->collisions +=
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(tdes3 & TDES3_COLLISION_COUNT_MASK)
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>> TDES3_COLLISION_COUNT_SHIFT;
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if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
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x->tx_deferred++;
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if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR))
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x->tx_underflow++;
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if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
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x->tx_ip_header_error++;
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if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
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x->tx_payload_error++;
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ret = tx_err;
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}
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if (unlikely(tdes3 & TDES3_DEFERRED))
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x->tx_deferred++;
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return ret;
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}
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static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p)
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{
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struct net_device_stats *stats = (struct net_device_stats *)data;
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unsigned int rdes1 = p->des1;
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unsigned int rdes2 = p->des2;
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unsigned int rdes3 = p->des3;
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int message_type;
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int ret = good_frame;
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if (unlikely(rdes3 & RDES3_OWN))
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return dma_own;
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/* Verify rx error by looking at the last segment. */
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if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
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return discard_frame;
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if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
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if (unlikely(rdes3 & RDES3_GIANT_PACKET))
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stats->rx_length_errors++;
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if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
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x->rx_gmac_overflow++;
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if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
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x->rx_watchdog++;
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if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
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x->rx_mii++;
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if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
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x->rx_crc++;
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stats->rx_crc_errors++;
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}
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if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
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x->dribbling_bit++;
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ret = discard_frame;
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}
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message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
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if (rdes1 & RDES1_IP_HDR_ERROR)
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x->ip_hdr_err++;
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if (rdes1 & RDES1_IP_CSUM_BYPASSED)
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x->ip_csum_bypassed++;
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if (rdes1 & RDES1_IPV4_HEADER)
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x->ipv4_pkt_rcvd++;
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if (rdes1 & RDES1_IPV6_HEADER)
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x->ipv6_pkt_rcvd++;
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if (message_type == RDES_EXT_SYNC)
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x->rx_msg_type_sync++;
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else if (message_type == RDES_EXT_FOLLOW_UP)
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x->rx_msg_type_follow_up++;
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else if (message_type == RDES_EXT_DELAY_REQ)
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x->rx_msg_type_delay_req++;
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else if (message_type == RDES_EXT_DELAY_RESP)
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x->rx_msg_type_delay_resp++;
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else if (message_type == RDES_EXT_PDELAY_REQ)
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x->rx_msg_type_pdelay_req++;
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else if (message_type == RDES_EXT_PDELAY_RESP)
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x->rx_msg_type_pdelay_resp++;
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else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
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x->rx_msg_type_pdelay_follow_up++;
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else
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x->rx_msg_type_ext_no_ptp++;
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if (rdes1 & RDES1_PTP_PACKET_TYPE)
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x->ptp_frame_type++;
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if (rdes1 & RDES1_PTP_VER)
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x->ptp_ver++;
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if (rdes1 & RDES1_TIMESTAMP_DROPPED)
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x->timestamp_dropped++;
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if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
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x->sa_rx_filter_fail++;
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ret = discard_frame;
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}
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if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
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x->da_rx_filter_fail++;
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ret = discard_frame;
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}
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if (rdes2 & RDES2_L3_FILTER_MATCH)
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x->l3_filter_match++;
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if (rdes2 & RDES2_L4_FILTER_MATCH)
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x->l4_filter_match++;
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if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
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>> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
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x->l3_l4_filter_no_match++;
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return ret;
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}
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static int dwmac4_rd_get_tx_len(struct dma_desc *p)
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{
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return (p->des2 & TDES2_BUFFER1_SIZE_MASK);
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}
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static int dwmac4_get_tx_owner(struct dma_desc *p)
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{
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return (p->des3 & TDES3_OWN) >> TDES3_OWN_SHIFT;
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}
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static void dwmac4_set_tx_owner(struct dma_desc *p)
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{
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p->des3 |= TDES3_OWN;
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}
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static void dwmac4_set_rx_owner(struct dma_desc *p)
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{
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p->des3 |= RDES3_OWN;
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}
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static int dwmac4_get_tx_ls(struct dma_desc *p)
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{
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return (p->des3 & TDES3_LAST_DESCRIPTOR) >> TDES3_LAST_DESCRIPTOR_SHIFT;
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}
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static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
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{
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return (p->des3 & RDES3_PACKET_SIZE_MASK);
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}
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static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
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{
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p->des2 |= TDES2_TIMESTAMP_ENABLE;
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}
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static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
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{
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return (p->des3 & TDES3_TIMESTAMP_STATUS)
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>> TDES3_TIMESTAMP_STATUS_SHIFT;
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}
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/* NOTE: For RX CTX bit has to be checked before
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* HAVE a specific function for TX and another one for RX
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*/
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static u64 dwmac4_wrback_get_timestamp(void *desc, u32 ats)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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u64 ns;
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ns = p->des0;
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/* convert high/sec time stamp value to nanosecond */
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ns += p->des1 * 1000000000ULL;
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return ns;
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}
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static int dwmac4_context_get_rx_timestamp_status(void *desc, u32 ats)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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return (p->des1 & RDES1_TIMESTAMP_AVAILABLE)
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>> RDES1_TIMESTAMP_AVAILABLE_SHIFT;
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}
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static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
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int mode, int end)
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{
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p->des3 = RDES3_OWN | RDES3_BUFFER1_VALID_ADDR;
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if (!disable_rx_ic)
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p->des3 |= RDES3_INT_ON_COMPLETION_EN;
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}
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static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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}
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static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
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bool csum_flag, int mode, bool tx_own,
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bool ls)
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{
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unsigned int tdes3 = p->des3;
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p->des2 |= (len & TDES2_BUFFER1_SIZE_MASK);
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if (is_fs)
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tdes3 |= TDES3_FIRST_DESCRIPTOR;
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else
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tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
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if (likely(csum_flag))
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tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
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else
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tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
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if (ls)
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tdes3 |= TDES3_LAST_DESCRIPTOR;
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else
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tdes3 &= ~TDES3_LAST_DESCRIPTOR;
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/* Finally set the OWN bit. Later the DMA will start! */
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if (tx_own)
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tdes3 |= TDES3_OWN;
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if (is_fs & tx_own)
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/* When the own bit, for the first frame, has to be set, all
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* descriptors for the same frame has to be set before, to
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* avoid race condition.
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*/
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wmb();
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p->des3 = tdes3;
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}
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static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
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int len1, int len2, bool tx_own,
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bool ls, unsigned int tcphdrlen,
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unsigned int tcppayloadlen)
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{
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unsigned int tdes3 = p->des3;
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if (len1)
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p->des2 |= (len1 & TDES2_BUFFER1_SIZE_MASK);
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if (len2)
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p->des2 |= (len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
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& TDES2_BUFFER2_SIZE_MASK;
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if (is_fs) {
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tdes3 |= TDES3_FIRST_DESCRIPTOR |
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TDES3_TCP_SEGMENTATION_ENABLE |
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((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
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TDES3_SLOT_NUMBER_MASK) |
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((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
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} else {
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tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
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}
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if (ls)
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tdes3 |= TDES3_LAST_DESCRIPTOR;
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else
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tdes3 &= ~TDES3_LAST_DESCRIPTOR;
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/* Finally set the OWN bit. Later the DMA will start! */
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if (tx_own)
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tdes3 |= TDES3_OWN;
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if (is_fs & tx_own)
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/* When the own bit, for the first frame, has to be set, all
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* descriptors for the same frame has to be set before, to
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* avoid race condition.
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*/
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wmb();
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p->des3 = tdes3;
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}
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static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
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{
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p->des2 = 0;
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p->des3 = 0;
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}
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static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
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{
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p->des2 |= TDES2_INTERRUPT_ON_COMPLETION;
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}
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static void dwmac4_display_ring(void *head, unsigned int size, bool rx)
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{
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struct dma_desc *p = (struct dma_desc *)head;
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int i;
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pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
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for (i = 0; i < size; i++) {
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if (p->des0)
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pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
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i, (unsigned int)virt_to_phys(p),
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p->des0, p->des1, p->des2, p->des3);
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p++;
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}
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}
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static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = mss;
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p->des3 = TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV;
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}
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const struct stmmac_desc_ops dwmac4_desc_ops = {
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.tx_status = dwmac4_wrback_get_tx_status,
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.rx_status = dwmac4_wrback_get_rx_status,
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.get_tx_len = dwmac4_rd_get_tx_len,
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.get_tx_owner = dwmac4_get_tx_owner,
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.set_tx_owner = dwmac4_set_tx_owner,
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.set_rx_owner = dwmac4_set_rx_owner,
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.get_tx_ls = dwmac4_get_tx_ls,
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.get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
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.enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
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.get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
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.get_timestamp = dwmac4_wrback_get_timestamp,
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.get_rx_timestamp_status = dwmac4_context_get_rx_timestamp_status,
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.set_tx_ic = dwmac4_rd_set_tx_ic,
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.prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
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.prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
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.release_tx_desc = dwmac4_release_tx_desc,
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.init_rx_desc = dwmac4_rd_init_rx_desc,
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.init_tx_desc = dwmac4_rd_init_tx_desc,
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.display_ring = dwmac4_display_ring,
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.set_mss = dwmac4_set_mss_ctxt,
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};
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const struct stmmac_mode_ops dwmac4_ring_mode_ops = { };
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