458 lines
12 KiB
C
458 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* BCM6328 USBH PHY Controller Driver
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*
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* Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
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* Copyright (C) 2015 Simon Arlott
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*
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* Derived from bcm963xx_4.12L.06B_consumer/kernel/linux/arch/mips/bcm963xx/setup.c:
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* Copyright (C) 2002 Broadcom Corporation
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*
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* Derived from OpenWrt patches:
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* Copyright (C) 2013 Jonas Gorski <jonas.gorski@gmail.com>
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* Copyright (C) 2013 Florian Fainelli <f.fainelli@gmail.com>
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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/* USBH control register offsets */
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enum usbh_regs {
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USBH_BRT_CONTROL1 = 0,
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USBH_BRT_CONTROL2,
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USBH_BRT_STATUS1,
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USBH_BRT_STATUS2,
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USBH_UTMI_CONTROL1,
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#define USBH_UC1_DEV_MODE_SEL BIT(0)
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USBH_TEST_PORT_CONTROL,
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USBH_PLL_CONTROL1,
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#define USBH_PLLC_REFCLKSEL_SHIFT 0
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#define USBH_PLLC_REFCLKSEL_MASK (0x3 << USBH_PLLC_REFCLKSEL_SHIFT)
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#define USBH_PLLC_CLKSEL_SHIFT 2
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#define USBH_PLLC_CLKSEL_MASK (0x3 << USBH_PLLC_CLKSEL_MASK)
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#define USBH_PLLC_XTAL_PWRDWNB BIT(4)
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#define USBH_PLLC_PLL_PWRDWNB BIT(5)
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#define USBH_PLLC_PLL_CALEN BIT(6)
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#define USBH_PLLC_PHYPLL_BYP BIT(7)
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#define USBH_PLLC_PLL_RESET BIT(8)
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#define USBH_PLLC_PLL_IDDQ_PWRDN BIT(9)
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#define USBH_PLLC_PLL_PWRDN_DELAY BIT(10)
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#define USBH_6318_PLLC_PLL_SUSPEND_EN BIT(27)
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#define USBH_6318_PLLC_PHYPLL_BYP BIT(29)
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#define USBH_6318_PLLC_PLL_RESET BIT(30)
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#define USBH_6318_PLLC_PLL_IDDQ_PWRDN BIT(31)
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USBH_SWAP_CONTROL,
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#define USBH_SC_OHCI_DATA_SWAP BIT(0)
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#define USBH_SC_OHCI_ENDIAN_SWAP BIT(1)
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#define USBH_SC_OHCI_LOGICAL_ADDR_EN BIT(2)
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#define USBH_SC_EHCI_DATA_SWAP BIT(3)
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#define USBH_SC_EHCI_ENDIAN_SWAP BIT(4)
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#define USBH_SC_EHCI_LOGICAL_ADDR_EN BIT(5)
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#define USBH_SC_USB_DEVICE_SEL BIT(6)
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USBH_GENERIC_CONTROL,
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#define USBH_GC_PLL_SUSPEND_EN BIT(1)
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USBH_FRAME_ADJUST_VALUE,
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USBH_SETUP,
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#define USBH_S_IOC BIT(4)
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#define USBH_S_IPP BIT(5)
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USBH_MDIO,
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USBH_MDIO32,
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USBH_USB_SIM_CONTROL,
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#define USBH_USC_LADDR_SEL BIT(5)
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__USBH_ENUM_SIZE
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};
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struct bcm63xx_usbh_phy_variant {
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/* Registers */
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long regs[__USBH_ENUM_SIZE];
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/* PLLC bits to set/clear for power on */
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u32 power_pllc_clr;
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u32 power_pllc_set;
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/* Setup bits to set/clear for power on */
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u32 setup_clr;
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u32 setup_set;
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/* Swap Control bits to set */
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u32 swapctl_dev_set;
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/* Test Port Control value to set if non-zero */
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u32 tpc_val;
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/* USB Sim Control bits to set */
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u32 usc_set;
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/* UTMI Control 1 bits to set */
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u32 utmictl1_dev_set;
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};
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struct bcm63xx_usbh_phy {
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void __iomem *base;
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struct clk *usbh_clk;
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struct clk *usb_ref_clk;
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struct reset_control *reset;
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const struct bcm63xx_usbh_phy_variant *variant;
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bool device_mode;
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};
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static const struct bcm63xx_usbh_phy_variant usbh_bcm6318 = {
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.regs = {
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[USBH_BRT_CONTROL1] = -1,
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[USBH_BRT_CONTROL2] = -1,
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[USBH_BRT_STATUS1] = -1,
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[USBH_BRT_STATUS2] = -1,
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[USBH_UTMI_CONTROL1] = 0x2c,
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[USBH_TEST_PORT_CONTROL] = 0x1c,
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[USBH_PLL_CONTROL1] = 0x04,
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[USBH_SWAP_CONTROL] = 0x0c,
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[USBH_GENERIC_CONTROL] = -1,
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[USBH_FRAME_ADJUST_VALUE] = 0x08,
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[USBH_SETUP] = 0x00,
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[USBH_MDIO] = 0x14,
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[USBH_MDIO32] = 0x18,
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[USBH_USB_SIM_CONTROL] = 0x20,
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},
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.power_pllc_clr = USBH_6318_PLLC_PLL_IDDQ_PWRDN,
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.power_pllc_set = USBH_6318_PLLC_PLL_SUSPEND_EN,
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.setup_set = USBH_S_IOC,
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.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
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.usc_set = USBH_USC_LADDR_SEL,
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.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
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};
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static const struct bcm63xx_usbh_phy_variant usbh_bcm6328 = {
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.regs = {
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[USBH_BRT_CONTROL1] = 0x00,
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[USBH_BRT_CONTROL2] = 0x04,
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[USBH_BRT_STATUS1] = 0x08,
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[USBH_BRT_STATUS2] = 0x0c,
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[USBH_UTMI_CONTROL1] = 0x10,
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[USBH_TEST_PORT_CONTROL] = 0x14,
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[USBH_PLL_CONTROL1] = 0x18,
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[USBH_SWAP_CONTROL] = 0x1c,
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[USBH_GENERIC_CONTROL] = 0x20,
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[USBH_FRAME_ADJUST_VALUE] = 0x24,
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[USBH_SETUP] = 0x28,
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[USBH_MDIO] = 0x2c,
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[USBH_MDIO32] = 0x30,
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[USBH_USB_SIM_CONTROL] = 0x34,
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},
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.setup_set = USBH_S_IOC,
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.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
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.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
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};
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static const struct bcm63xx_usbh_phy_variant usbh_bcm6358 = {
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.regs = {
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[USBH_BRT_CONTROL1] = -1,
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[USBH_BRT_CONTROL2] = -1,
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[USBH_BRT_STATUS1] = -1,
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[USBH_BRT_STATUS2] = -1,
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[USBH_UTMI_CONTROL1] = -1,
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[USBH_TEST_PORT_CONTROL] = 0x24,
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[USBH_PLL_CONTROL1] = -1,
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[USBH_SWAP_CONTROL] = 0x00,
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[USBH_GENERIC_CONTROL] = -1,
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[USBH_FRAME_ADJUST_VALUE] = -1,
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[USBH_SETUP] = -1,
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[USBH_MDIO] = -1,
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[USBH_MDIO32] = -1,
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[USBH_USB_SIM_CONTROL] = -1,
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},
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/*
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* The magic value comes for the original vendor BSP
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* and is needed for USB to work. Datasheet does not
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* help, so the magic value is used as-is.
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*/
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.tpc_val = 0x1c0020,
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};
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static const struct bcm63xx_usbh_phy_variant usbh_bcm6368 = {
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.regs = {
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[USBH_BRT_CONTROL1] = 0x00,
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[USBH_BRT_CONTROL2] = 0x04,
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[USBH_BRT_STATUS1] = 0x08,
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[USBH_BRT_STATUS2] = 0x0c,
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[USBH_UTMI_CONTROL1] = 0x10,
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[USBH_TEST_PORT_CONTROL] = 0x14,
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[USBH_PLL_CONTROL1] = 0x18,
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[USBH_SWAP_CONTROL] = 0x1c,
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[USBH_GENERIC_CONTROL] = -1,
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[USBH_FRAME_ADJUST_VALUE] = 0x24,
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[USBH_SETUP] = 0x28,
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[USBH_MDIO] = 0x2c,
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[USBH_MDIO32] = 0x30,
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[USBH_USB_SIM_CONTROL] = 0x34,
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},
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.power_pllc_clr = USBH_PLLC_PLL_IDDQ_PWRDN | USBH_PLLC_PLL_PWRDN_DELAY,
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.setup_set = USBH_S_IOC,
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.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
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.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
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};
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static const struct bcm63xx_usbh_phy_variant usbh_bcm63268 = {
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.regs = {
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[USBH_BRT_CONTROL1] = 0x00,
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[USBH_BRT_CONTROL2] = 0x04,
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[USBH_BRT_STATUS1] = 0x08,
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[USBH_BRT_STATUS2] = 0x0c,
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[USBH_UTMI_CONTROL1] = 0x10,
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[USBH_TEST_PORT_CONTROL] = 0x14,
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[USBH_PLL_CONTROL1] = 0x18,
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[USBH_SWAP_CONTROL] = 0x1c,
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[USBH_GENERIC_CONTROL] = 0x20,
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[USBH_FRAME_ADJUST_VALUE] = 0x24,
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[USBH_SETUP] = 0x28,
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[USBH_MDIO] = 0x2c,
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[USBH_MDIO32] = 0x30,
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[USBH_USB_SIM_CONTROL] = 0x34,
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},
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.power_pllc_clr = USBH_PLLC_PLL_IDDQ_PWRDN | USBH_PLLC_PLL_PWRDN_DELAY,
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.setup_clr = USBH_S_IPP,
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.setup_set = USBH_S_IOC,
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.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
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.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
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};
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static inline bool usbh_has_reg(struct bcm63xx_usbh_phy *usbh, int reg)
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{
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return (usbh->variant->regs[reg] >= 0);
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}
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static inline u32 usbh_readl(struct bcm63xx_usbh_phy *usbh, int reg)
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{
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return __raw_readl(usbh->base + usbh->variant->regs[reg]);
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}
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static inline void usbh_writel(struct bcm63xx_usbh_phy *usbh, int reg,
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u32 value)
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{
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__raw_writel(value, usbh->base + usbh->variant->regs[reg]);
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}
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static int bcm63xx_usbh_phy_init(struct phy *phy)
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{
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struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
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int ret;
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ret = clk_prepare_enable(usbh->usbh_clk);
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if (ret) {
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dev_err(&phy->dev, "unable to enable usbh clock: %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(usbh->usb_ref_clk);
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if (ret) {
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dev_err(&phy->dev, "unable to enable usb_ref clock: %d\n", ret);
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clk_disable_unprepare(usbh->usbh_clk);
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return ret;
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}
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ret = reset_control_reset(usbh->reset);
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if (ret) {
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dev_err(&phy->dev, "unable to reset device: %d\n", ret);
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clk_disable_unprepare(usbh->usb_ref_clk);
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clk_disable_unprepare(usbh->usbh_clk);
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return ret;
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}
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/* Configure to work in native CPU endian */
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if (usbh_has_reg(usbh, USBH_SWAP_CONTROL)) {
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u32 val = usbh_readl(usbh, USBH_SWAP_CONTROL);
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val |= USBH_SC_EHCI_DATA_SWAP;
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val &= ~USBH_SC_EHCI_ENDIAN_SWAP;
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val |= USBH_SC_OHCI_DATA_SWAP;
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val &= ~USBH_SC_OHCI_ENDIAN_SWAP;
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if (usbh->device_mode && usbh->variant->swapctl_dev_set)
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val |= usbh->variant->swapctl_dev_set;
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usbh_writel(usbh, USBH_SWAP_CONTROL, val);
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}
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if (usbh_has_reg(usbh, USBH_SETUP)) {
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u32 val = usbh_readl(usbh, USBH_SETUP);
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val |= usbh->variant->setup_set;
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val &= ~usbh->variant->setup_clr;
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usbh_writel(usbh, USBH_SETUP, val);
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}
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if (usbh_has_reg(usbh, USBH_USB_SIM_CONTROL)) {
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u32 val = usbh_readl(usbh, USBH_USB_SIM_CONTROL);
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val |= usbh->variant->usc_set;
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usbh_writel(usbh, USBH_USB_SIM_CONTROL, val);
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}
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if (usbh->variant->tpc_val &&
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usbh_has_reg(usbh, USBH_TEST_PORT_CONTROL))
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usbh_writel(usbh, USBH_TEST_PORT_CONTROL,
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usbh->variant->tpc_val);
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if (usbh->device_mode &&
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usbh_has_reg(usbh, USBH_UTMI_CONTROL1) &&
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usbh->variant->utmictl1_dev_set) {
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u32 val = usbh_readl(usbh, USBH_UTMI_CONTROL1);
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val |= usbh->variant->utmictl1_dev_set;
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usbh_writel(usbh, USBH_UTMI_CONTROL1, val);
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}
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return 0;
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}
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static int bcm63xx_usbh_phy_power_on(struct phy *phy)
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{
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struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
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if (usbh_has_reg(usbh, USBH_PLL_CONTROL1)) {
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u32 val = usbh_readl(usbh, USBH_PLL_CONTROL1);
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val |= usbh->variant->power_pllc_set;
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val &= ~usbh->variant->power_pllc_clr;
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usbh_writel(usbh, USBH_PLL_CONTROL1, val);
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}
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return 0;
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}
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static int bcm63xx_usbh_phy_power_off(struct phy *phy)
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{
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struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
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if (usbh_has_reg(usbh, USBH_PLL_CONTROL1)) {
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u32 val = usbh_readl(usbh, USBH_PLL_CONTROL1);
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val &= ~usbh->variant->power_pllc_set;
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val |= usbh->variant->power_pllc_clr;
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usbh_writel(usbh, USBH_PLL_CONTROL1, val);
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}
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return 0;
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}
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static int bcm63xx_usbh_phy_exit(struct phy *phy)
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{
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struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
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clk_disable_unprepare(usbh->usbh_clk);
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clk_disable_unprepare(usbh->usb_ref_clk);
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return 0;
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}
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static const struct phy_ops bcm63xx_usbh_phy_ops = {
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.exit = bcm63xx_usbh_phy_exit,
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.init = bcm63xx_usbh_phy_init,
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.power_off = bcm63xx_usbh_phy_power_off,
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.power_on = bcm63xx_usbh_phy_power_on,
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.owner = THIS_MODULE,
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};
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static struct phy *bcm63xx_usbh_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct bcm63xx_usbh_phy *usbh = dev_get_drvdata(dev);
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usbh->device_mode = !!args->args[0];
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return of_phy_simple_xlate(dev, args);
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}
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static int __init bcm63xx_usbh_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct bcm63xx_usbh_phy *usbh;
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const struct bcm63xx_usbh_phy_variant *variant;
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struct phy *phy;
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struct phy_provider *phy_provider;
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usbh = devm_kzalloc(dev, sizeof(*usbh), GFP_KERNEL);
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if (!usbh)
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return -ENOMEM;
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variant = device_get_match_data(dev);
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if (!variant)
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return -EINVAL;
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usbh->variant = variant;
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usbh->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(usbh->base))
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return PTR_ERR(usbh->base);
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usbh->reset = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(usbh->reset)) {
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if (PTR_ERR(usbh->reset) != -EPROBE_DEFER)
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dev_err(dev, "failed to get reset\n");
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return PTR_ERR(usbh->reset);
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}
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usbh->usbh_clk = devm_clk_get_optional(dev, "usbh");
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if (IS_ERR(usbh->usbh_clk))
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return PTR_ERR(usbh->usbh_clk);
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usbh->usb_ref_clk = devm_clk_get_optional(dev, "usb_ref");
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if (IS_ERR(usbh->usb_ref_clk))
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return PTR_ERR(usbh->usb_ref_clk);
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phy = devm_phy_create(dev, NULL, &bcm63xx_usbh_phy_ops);
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if (IS_ERR(phy)) {
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dev_err(dev, "failed to create PHY\n");
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return PTR_ERR(phy);
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}
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platform_set_drvdata(pdev, usbh);
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phy_set_drvdata(phy, usbh);
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phy_provider = devm_of_phy_provider_register(dev,
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bcm63xx_usbh_phy_xlate);
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if (IS_ERR(phy_provider)) {
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dev_err(dev, "failed to register PHY provider\n");
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return PTR_ERR(phy_provider);
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}
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dev_dbg(dev, "Registered BCM63xx USB PHY driver\n");
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return 0;
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}
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static const struct of_device_id bcm63xx_usbh_phy_ids[] __initconst = {
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{ .compatible = "brcm,bcm6318-usbh-phy", .data = &usbh_bcm6318 },
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{ .compatible = "brcm,bcm6328-usbh-phy", .data = &usbh_bcm6328 },
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{ .compatible = "brcm,bcm6358-usbh-phy", .data = &usbh_bcm6358 },
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{ .compatible = "brcm,bcm6362-usbh-phy", .data = &usbh_bcm6368 },
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{ .compatible = "brcm,bcm6368-usbh-phy", .data = &usbh_bcm6368 },
|
|
{ .compatible = "brcm,bcm63268-usbh-phy", .data = &usbh_bcm63268 },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, bcm63xx_usbh_phy_ids);
|
|
|
|
static struct platform_driver bcm63xx_usbh_phy_driver __refdata = {
|
|
.driver = {
|
|
.name = "bcm63xx-usbh-phy",
|
|
.of_match_table = bcm63xx_usbh_phy_ids,
|
|
},
|
|
.probe = bcm63xx_usbh_phy_probe,
|
|
};
|
|
module_platform_driver(bcm63xx_usbh_phy_driver);
|
|
|
|
MODULE_DESCRIPTION("BCM63xx USBH PHY driver");
|
|
MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>");
|
|
MODULE_AUTHOR("Simon Arlott");
|
|
MODULE_LICENSE("GPL");
|