338 lines
9.0 KiB
C
338 lines
9.0 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*/
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/hugetlb.h>
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#include <asm/tlbflush.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s.h>
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#include <asm/mmu-hash64.h>
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#include <asm/hvcall.h>
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#include <asm/synch.h>
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#include <asm/ppc-opcode.h>
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/* For now use fixed-size 16MB page table */
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#define HPT_ORDER 24
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#define HPT_NPTEG (1ul << (HPT_ORDER - 7)) /* 128B per pteg */
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#define HPT_HASH_MASK (HPT_NPTEG - 1)
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#define HPTE_V_HVLOCK 0x40UL
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static inline long lock_hpte(unsigned long *hpte, unsigned long bits)
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{
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unsigned long tmp, old;
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asm volatile(" ldarx %0,0,%2\n"
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" and. %1,%0,%3\n"
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" bne 2f\n"
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" ori %0,%0,%4\n"
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" stdcx. %0,0,%2\n"
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" beq+ 2f\n"
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" li %1,%3\n"
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"2: isync"
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: "=&r" (tmp), "=&r" (old)
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: "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
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: "cc", "memory");
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return old == 0;
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}
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long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
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long pte_index, unsigned long pteh, unsigned long ptel)
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{
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unsigned long porder;
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struct kvm *kvm = vcpu->kvm;
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unsigned long i, lpn, pa;
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unsigned long *hpte;
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/* only handle 4k, 64k and 16M pages for now */
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porder = 12;
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if (pteh & HPTE_V_LARGE) {
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if (cpu_has_feature(CPU_FTR_ARCH_206) &&
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(ptel & 0xf000) == 0x1000) {
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/* 64k page */
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porder = 16;
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} else if ((ptel & 0xff000) == 0) {
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/* 16M page */
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porder = 24;
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/* lowest AVA bit must be 0 for 16M pages */
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if (pteh & 0x80)
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return H_PARAMETER;
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} else
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return H_PARAMETER;
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}
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lpn = (ptel & HPTE_R_RPN) >> kvm->arch.ram_porder;
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if (lpn >= kvm->arch.ram_npages || porder > kvm->arch.ram_porder)
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return H_PARAMETER;
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pa = kvm->arch.ram_pginfo[lpn].pfn << PAGE_SHIFT;
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if (!pa)
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return H_PARAMETER;
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/* Check WIMG */
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if ((ptel & HPTE_R_WIMG) != HPTE_R_M &&
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(ptel & HPTE_R_WIMG) != (HPTE_R_W | HPTE_R_I | HPTE_R_M))
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return H_PARAMETER;
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pteh &= ~0x60UL;
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ptel &= ~(HPTE_R_PP0 - kvm->arch.ram_psize);
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ptel |= pa;
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if (pte_index >= (HPT_NPTEG << 3))
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return H_PARAMETER;
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if (likely((flags & H_EXACT) == 0)) {
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pte_index &= ~7UL;
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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for (i = 0; ; ++i) {
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if (i == 8)
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return H_PTEG_FULL;
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if ((*hpte & HPTE_V_VALID) == 0 &&
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lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID))
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break;
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hpte += 2;
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}
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} else {
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i = 0;
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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if (!lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID))
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return H_PTEG_FULL;
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}
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hpte[1] = ptel;
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eieio();
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hpte[0] = pteh;
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asm volatile("ptesync" : : : "memory");
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atomic_inc(&kvm->arch.ram_pginfo[lpn].refcnt);
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vcpu->arch.gpr[4] = pte_index + i;
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return H_SUCCESS;
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}
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#define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
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static inline int try_lock_tlbie(unsigned int *lock)
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{
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unsigned int tmp, old;
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unsigned int token = LOCK_TOKEN;
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asm volatile("1:lwarx %1,0,%2\n"
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" cmpwi cr0,%1,0\n"
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" bne 2f\n"
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" stwcx. %3,0,%2\n"
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" bne- 1b\n"
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" isync\n"
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"2:"
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: "=&r" (tmp), "=&r" (old)
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: "r" (lock), "r" (token)
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: "cc", "memory");
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return old == 0;
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}
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long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
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unsigned long pte_index, unsigned long avpn,
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unsigned long va)
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{
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struct kvm *kvm = vcpu->kvm;
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unsigned long *hpte;
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unsigned long v, r, rb;
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if (pte_index >= (HPT_NPTEG << 3))
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return H_PARAMETER;
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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while (!lock_hpte(hpte, HPTE_V_HVLOCK))
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cpu_relax();
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if ((hpte[0] & HPTE_V_VALID) == 0 ||
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((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn) ||
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((flags & H_ANDCOND) && (hpte[0] & avpn) != 0)) {
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hpte[0] &= ~HPTE_V_HVLOCK;
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return H_NOT_FOUND;
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}
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if (atomic_read(&kvm->online_vcpus) == 1)
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flags |= H_LOCAL;
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vcpu->arch.gpr[4] = v = hpte[0] & ~HPTE_V_HVLOCK;
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vcpu->arch.gpr[5] = r = hpte[1];
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rb = compute_tlbie_rb(v, r, pte_index);
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hpte[0] = 0;
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if (!(flags & H_LOCAL)) {
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while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
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cpu_relax();
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asm volatile("ptesync" : : : "memory");
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asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
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: : "r" (rb), "r" (kvm->arch.lpid));
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asm volatile("ptesync" : : : "memory");
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kvm->arch.tlbie_lock = 0;
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} else {
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asm volatile("ptesync" : : : "memory");
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asm volatile("tlbiel %0" : : "r" (rb));
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asm volatile("ptesync" : : : "memory");
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}
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return H_SUCCESS;
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}
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long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = vcpu->kvm;
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unsigned long *args = &vcpu->arch.gpr[4];
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unsigned long *hp, tlbrb[4];
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long int i, found;
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long int n_inval = 0;
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unsigned long flags, req, pte_index;
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long int local = 0;
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long int ret = H_SUCCESS;
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if (atomic_read(&kvm->online_vcpus) == 1)
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local = 1;
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for (i = 0; i < 4; ++i) {
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pte_index = args[i * 2];
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flags = pte_index >> 56;
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pte_index &= ((1ul << 56) - 1);
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req = flags >> 6;
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flags &= 3;
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if (req == 3)
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break;
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if (req != 1 || flags == 3 ||
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pte_index >= (HPT_NPTEG << 3)) {
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/* parameter error */
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args[i * 2] = ((0xa0 | flags) << 56) + pte_index;
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ret = H_PARAMETER;
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break;
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}
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hp = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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while (!lock_hpte(hp, HPTE_V_HVLOCK))
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cpu_relax();
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found = 0;
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if (hp[0] & HPTE_V_VALID) {
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switch (flags & 3) {
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case 0: /* absolute */
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found = 1;
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break;
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case 1: /* andcond */
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if (!(hp[0] & args[i * 2 + 1]))
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found = 1;
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break;
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case 2: /* AVPN */
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if ((hp[0] & ~0x7fUL) == args[i * 2 + 1])
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found = 1;
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break;
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}
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}
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if (!found) {
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hp[0] &= ~HPTE_V_HVLOCK;
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args[i * 2] = ((0x90 | flags) << 56) + pte_index;
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continue;
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}
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/* insert R and C bits from PTE */
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flags |= (hp[1] >> 5) & 0x0c;
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args[i * 2] = ((0x80 | flags) << 56) + pte_index;
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tlbrb[n_inval++] = compute_tlbie_rb(hp[0], hp[1], pte_index);
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hp[0] = 0;
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}
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if (n_inval == 0)
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return ret;
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if (!local) {
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while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
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cpu_relax();
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asm volatile("ptesync" : : : "memory");
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for (i = 0; i < n_inval; ++i)
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asm volatile(PPC_TLBIE(%1,%0)
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: : "r" (tlbrb[i]), "r" (kvm->arch.lpid));
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asm volatile("eieio; tlbsync; ptesync" : : : "memory");
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kvm->arch.tlbie_lock = 0;
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} else {
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asm volatile("ptesync" : : : "memory");
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for (i = 0; i < n_inval; ++i)
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asm volatile("tlbiel %0" : : "r" (tlbrb[i]));
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asm volatile("ptesync" : : : "memory");
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}
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return ret;
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}
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long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
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unsigned long pte_index, unsigned long avpn,
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unsigned long va)
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{
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struct kvm *kvm = vcpu->kvm;
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unsigned long *hpte;
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unsigned long v, r, rb;
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if (pte_index >= (HPT_NPTEG << 3))
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return H_PARAMETER;
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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while (!lock_hpte(hpte, HPTE_V_HVLOCK))
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cpu_relax();
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if ((hpte[0] & HPTE_V_VALID) == 0 ||
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((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn)) {
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hpte[0] &= ~HPTE_V_HVLOCK;
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return H_NOT_FOUND;
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}
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if (atomic_read(&kvm->online_vcpus) == 1)
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flags |= H_LOCAL;
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v = hpte[0];
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r = hpte[1] & ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
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HPTE_R_KEY_HI | HPTE_R_KEY_LO);
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r |= (flags << 55) & HPTE_R_PP0;
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r |= (flags << 48) & HPTE_R_KEY_HI;
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r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
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rb = compute_tlbie_rb(v, r, pte_index);
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hpte[0] = v & ~HPTE_V_VALID;
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if (!(flags & H_LOCAL)) {
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while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
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cpu_relax();
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asm volatile("ptesync" : : : "memory");
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asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
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: : "r" (rb), "r" (kvm->arch.lpid));
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asm volatile("ptesync" : : : "memory");
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kvm->arch.tlbie_lock = 0;
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} else {
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asm volatile("ptesync" : : : "memory");
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asm volatile("tlbiel %0" : : "r" (rb));
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asm volatile("ptesync" : : : "memory");
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}
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hpte[1] = r;
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eieio();
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hpte[0] = v & ~HPTE_V_HVLOCK;
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asm volatile("ptesync" : : : "memory");
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return H_SUCCESS;
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}
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static unsigned long reverse_xlate(struct kvm *kvm, unsigned long realaddr)
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{
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long int i;
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unsigned long offset, rpn;
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offset = realaddr & (kvm->arch.ram_psize - 1);
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rpn = (realaddr - offset) >> PAGE_SHIFT;
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for (i = 0; i < kvm->arch.ram_npages; ++i)
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if (rpn == kvm->arch.ram_pginfo[i].pfn)
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return (i << PAGE_SHIFT) + offset;
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return HPTE_R_RPN; /* all 1s in the RPN field */
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}
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long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
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unsigned long pte_index)
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{
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struct kvm *kvm = vcpu->kvm;
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unsigned long *hpte, r;
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int i, n = 1;
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if (pte_index >= (HPT_NPTEG << 3))
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return H_PARAMETER;
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if (flags & H_READ_4) {
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pte_index &= ~3;
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n = 4;
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}
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for (i = 0; i < n; ++i, ++pte_index) {
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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r = hpte[1];
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if ((flags & H_R_XLATE) && (hpte[0] & HPTE_V_VALID))
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r = reverse_xlate(kvm, r & HPTE_R_RPN) |
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(r & ~HPTE_R_RPN);
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vcpu->arch.gpr[4 + i * 2] = hpte[0];
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vcpu->arch.gpr[5 + i * 2] = r;
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}
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return H_SUCCESS;
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}
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