367 lines
9.7 KiB
C
367 lines
9.7 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include "amdgpu.h"
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#include "soc15_common.h"
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#include "nv.h"
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#include "gc/gc_10_1_0_offset.h"
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#include "gc/gc_10_1_0_sh_mask.h"
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MODULE_FIRMWARE("amdgpu/navi10_mes.bin");
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static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes,
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struct mes_add_queue_input *input)
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{
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return 0;
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}
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static int mes_v10_1_remove_hw_queue(struct amdgpu_mes *mes,
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struct mes_remove_queue_input *input)
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{
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return 0;
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}
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static int mes_v10_1_suspend_gang(struct amdgpu_mes *mes,
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struct mes_suspend_gang_input *input)
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{
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return 0;
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}
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static int mes_v10_1_resume_gang(struct amdgpu_mes *mes,
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struct mes_resume_gang_input *input)
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{
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return 0;
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}
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static const struct amdgpu_mes_funcs mes_v10_1_funcs = {
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.add_hw_queue = mes_v10_1_add_hw_queue,
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.remove_hw_queue = mes_v10_1_remove_hw_queue,
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.suspend_gang = mes_v10_1_suspend_gang,
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.resume_gang = mes_v10_1_resume_gang,
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};
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static int mes_v10_1_init_microcode(struct amdgpu_device *adev)
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{
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const char *chip_name;
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char fw_name[30];
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int err;
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const struct mes_firmware_header_v1_0 *mes_hdr;
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switch (adev->asic_type) {
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case CHIP_NAVI10:
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chip_name = "navi10";
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break;
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default:
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BUG();
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}
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", chip_name);
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err = request_firmware(&adev->mes.fw, fw_name, adev->dev);
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if (err)
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return err;
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err = amdgpu_ucode_validate(adev->mes.fw);
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if (err) {
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release_firmware(adev->mes.fw);
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adev->mes.fw = NULL;
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return err;
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}
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mes_hdr = (const struct mes_firmware_header_v1_0 *)adev->mes.fw->data;
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adev->mes.ucode_fw_version = le32_to_cpu(mes_hdr->mes_ucode_version);
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adev->mes.ucode_fw_version =
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le32_to_cpu(mes_hdr->mes_ucode_data_version);
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adev->mes.uc_start_addr =
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le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
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((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32);
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adev->mes.data_start_addr =
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le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
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((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
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return 0;
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}
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static void mes_v10_1_free_microcode(struct amdgpu_device *adev)
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{
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release_firmware(adev->mes.fw);
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adev->mes.fw = NULL;
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}
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static int mes_v10_1_allocate_ucode_buffer(struct amdgpu_device *adev)
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{
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int r;
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const struct mes_firmware_header_v1_0 *mes_hdr;
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const __le32 *fw_data;
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unsigned fw_size;
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mes_hdr = (const struct mes_firmware_header_v1_0 *)
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adev->mes.fw->data;
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fw_data = (const __le32 *)(adev->mes.fw->data +
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le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
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fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
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r = amdgpu_bo_create_reserved(adev, fw_size,
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
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&adev->mes.ucode_fw_obj,
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&adev->mes.ucode_fw_gpu_addr,
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(void **)&adev->mes.ucode_fw_ptr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
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return r;
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}
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memcpy(adev->mes.ucode_fw_ptr, fw_data, fw_size);
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amdgpu_bo_kunmap(adev->mes.ucode_fw_obj);
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amdgpu_bo_unreserve(adev->mes.ucode_fw_obj);
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return 0;
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}
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static int mes_v10_1_allocate_ucode_data_buffer(struct amdgpu_device *adev)
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{
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int r;
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const struct mes_firmware_header_v1_0 *mes_hdr;
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const __le32 *fw_data;
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unsigned fw_size;
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mes_hdr = (const struct mes_firmware_header_v1_0 *)
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adev->mes.fw->data;
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fw_data = (const __le32 *)(adev->mes.fw->data +
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le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
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fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
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r = amdgpu_bo_create_reserved(adev, fw_size,
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64 * 1024, AMDGPU_GEM_DOMAIN_GTT,
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&adev->mes.data_fw_obj,
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&adev->mes.data_fw_gpu_addr,
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(void **)&adev->mes.data_fw_ptr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
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return r;
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}
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memcpy(adev->mes.data_fw_ptr, fw_data, fw_size);
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amdgpu_bo_kunmap(adev->mes.data_fw_obj);
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amdgpu_bo_unreserve(adev->mes.data_fw_obj);
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return 0;
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}
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static void mes_v10_1_free_ucode_buffers(struct amdgpu_device *adev)
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{
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amdgpu_bo_free_kernel(&adev->mes.data_fw_obj,
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&adev->mes.data_fw_gpu_addr,
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(void **)&adev->mes.data_fw_ptr);
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amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj,
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&adev->mes.ucode_fw_gpu_addr,
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(void **)&adev->mes.ucode_fw_ptr);
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}
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static void mes_v10_1_enable(struct amdgpu_device *adev, bool enable)
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{
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uint32_t data = 0;
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if (enable) {
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data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL);
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data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
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WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);
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/* set ucode start address */
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WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,
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(uint32_t)(adev->mes.uc_start_addr) >> 2);
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/* clear BYPASS_UNCACHED to avoid hangs after interrupt. */
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data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL);
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data = REG_SET_FIELD(data, CP_MES_DC_OP_CNTL,
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BYPASS_UNCACHED, 0);
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WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data);
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/* unhalt MES and activate pipe0 */
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data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
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WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);
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} else {
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data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL);
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data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
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data = REG_SET_FIELD(data, CP_MES_CNTL,
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MES_INVALIDATE_ICACHE, 1);
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data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
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data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
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WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);
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}
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}
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/* This function is for backdoor MES firmware */
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static int mes_v10_1_load_microcode(struct amdgpu_device *adev)
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{
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int r;
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uint32_t data;
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if (!adev->mes.fw)
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return -EINVAL;
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r = mes_v10_1_allocate_ucode_buffer(adev);
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if (r)
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return r;
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r = mes_v10_1_allocate_ucode_data_buffer(adev);
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if (r) {
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mes_v10_1_free_ucode_buffers(adev);
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return r;
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}
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mes_v10_1_enable(adev, false);
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WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0);
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mutex_lock(&adev->srbm_mutex);
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/* me=3, pipe=0, queue=0 */
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nv_grbm_select(adev, 3, 0, 0, 0);
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/* set ucode start address */
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WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,
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(uint32_t)(adev->mes.uc_start_addr) >> 2);
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/* set ucode fimrware address */
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WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO,
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lower_32_bits(adev->mes.ucode_fw_gpu_addr));
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WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI,
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upper_32_bits(adev->mes.ucode_fw_gpu_addr));
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/* set ucode instruction cache boundary to 2M-1 */
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WREG32_SOC15(GC, 0, mmCP_MES_MIBOUND_LO, 0x1FFFFF);
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/* set ucode data firmware address */
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WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_LO,
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lower_32_bits(adev->mes.data_fw_gpu_addr));
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WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_HI,
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upper_32_bits(adev->mes.data_fw_gpu_addr));
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/* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
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WREG32_SOC15(GC, 0, mmCP_MES_MDBOUND_LO, 0x3FFFF);
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/* invalidate ICACHE */
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data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
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data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
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data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
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WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
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/* prime the ICACHE. */
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data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL);
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data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
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WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data);
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nv_grbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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return 0;
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}
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static int mes_v10_1_sw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = mes_v10_1_init_microcode(adev);
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if (r)
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return r;
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return 0;
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}
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static int mes_v10_1_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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mes_v10_1_free_microcode(adev);
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return 0;
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}
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static int mes_v10_1_hw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
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r = mes_v10_1_load_microcode(adev);
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if (r) {
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DRM_ERROR("failed to MES fw, r=%d\n", r);
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return r;
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}
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} else {
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DRM_ERROR("only support direct fw loading on MES\n");
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return -EINVAL;
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}
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mes_v10_1_enable(adev, true);
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return 0;
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}
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static int mes_v10_1_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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mes_v10_1_enable(adev, false);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
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mes_v10_1_free_ucode_buffers(adev);
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return 0;
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}
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static int mes_v10_1_suspend(void *handle)
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{
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return 0;
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}
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static int mes_v10_1_resume(void *handle)
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{
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return 0;
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}
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static const struct amd_ip_funcs mes_v10_1_ip_funcs = {
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.name = "mes_v10_1",
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.sw_init = mes_v10_1_sw_init,
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.sw_fini = mes_v10_1_sw_fini,
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.hw_init = mes_v10_1_hw_init,
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.hw_fini = mes_v10_1_hw_fini,
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.suspend = mes_v10_1_suspend,
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.resume = mes_v10_1_resume,
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};
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const struct amdgpu_ip_block_version mes_v10_1_ip_block = {
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.type = AMD_IP_BLOCK_TYPE_MES,
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.major = 10,
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.minor = 1,
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.rev = 0,
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.funcs = &mes_v10_1_ip_funcs,
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};
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