357 lines
9.1 KiB
C
357 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Bluefield-specific EDAC driver.
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*
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* Copyright (c) 2019 Mellanox Technologies.
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*/
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#include <linux/acpi.h>
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#include <linux/arm-smccc.h>
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#include <linux/bitfield.h>
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#include <linux/edac.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "edac_module.h"
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#define DRIVER_NAME "bluefield-edac"
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/*
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* Mellanox BlueField EMI (External Memory Interface) register definitions.
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*/
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#define MLXBF_ECC_CNT 0x340
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#define MLXBF_ECC_CNT__SERR_CNT GENMASK(15, 0)
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#define MLXBF_ECC_CNT__DERR_CNT GENMASK(31, 16)
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#define MLXBF_ECC_ERR 0x348
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#define MLXBF_ECC_ERR__SECC BIT(0)
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#define MLXBF_ECC_ERR__DECC BIT(16)
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#define MLXBF_ECC_LATCH_SEL 0x354
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#define MLXBF_ECC_LATCH_SEL__START BIT(24)
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#define MLXBF_ERR_ADDR_0 0x358
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#define MLXBF_ERR_ADDR_1 0x37c
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#define MLXBF_SYNDROM 0x35c
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#define MLXBF_SYNDROM__DERR BIT(0)
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#define MLXBF_SYNDROM__SERR BIT(1)
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#define MLXBF_SYNDROM__SYN GENMASK(25, 16)
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#define MLXBF_ADD_INFO 0x364
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#define MLXBF_ADD_INFO__ERR_PRANK GENMASK(9, 8)
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#define MLXBF_EDAC_MAX_DIMM_PER_MC 2
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#define MLXBF_EDAC_ERROR_GRAIN 8
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/*
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* Request MLNX_SIP_GET_DIMM_INFO
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*
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* Retrieve information about DIMM on a certain slot.
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*
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* Call register usage:
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* a0: MLNX_SIP_GET_DIMM_INFO
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* a1: (Memory controller index) << 16 | (Dimm index in memory controller)
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* a2-7: not used.
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*
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* Return status:
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* a0: MLXBF_DIMM_INFO defined below describing the DIMM.
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* a1-3: not used.
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*/
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#define MLNX_SIP_GET_DIMM_INFO 0x82000008
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/* Format for the SMC response about the memory information */
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#define MLXBF_DIMM_INFO__SIZE_GB GENMASK_ULL(15, 0)
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#define MLXBF_DIMM_INFO__IS_RDIMM BIT(16)
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#define MLXBF_DIMM_INFO__IS_LRDIMM BIT(17)
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#define MLXBF_DIMM_INFO__IS_NVDIMM BIT(18)
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#define MLXBF_DIMM_INFO__RANKS GENMASK_ULL(23, 21)
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#define MLXBF_DIMM_INFO__PACKAGE_X GENMASK_ULL(31, 24)
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struct bluefield_edac_priv {
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int dimm_ranks[MLXBF_EDAC_MAX_DIMM_PER_MC];
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void __iomem *emi_base;
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int dimm_per_mc;
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};
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static u64 smc_call1(u64 smc_op, u64 smc_arg)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(smc_op, smc_arg, 0, 0, 0, 0, 0, 0, &res);
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return res.a0;
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}
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/*
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* Gather the ECC information from the External Memory Interface registers
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* and report it to the edac handler.
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*/
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static void bluefield_gather_report_ecc(struct mem_ctl_info *mci,
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int error_cnt,
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int is_single_ecc)
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{
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struct bluefield_edac_priv *priv = mci->pvt_info;
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u32 dram_additional_info, err_prank, edea0, edea1;
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u32 ecc_latch_select, dram_syndrom, serr, derr, syndrom;
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enum hw_event_mc_err_type ecc_type;
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u64 ecc_dimm_addr;
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int ecc_dimm;
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ecc_type = is_single_ecc ? HW_EVENT_ERR_CORRECTED :
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HW_EVENT_ERR_UNCORRECTED;
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/*
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* Tell the External Memory Interface to populate the relevant
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* registers with information about the last ECC error occurrence.
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*/
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ecc_latch_select = MLXBF_ECC_LATCH_SEL__START;
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writel(ecc_latch_select, priv->emi_base + MLXBF_ECC_LATCH_SEL);
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/*
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* Verify that the ECC reported info in the registers is of the
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* same type as the one asked to report. If not, just report the
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* error without the detailed information.
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*/
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dram_syndrom = readl(priv->emi_base + MLXBF_SYNDROM);
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serr = FIELD_GET(MLXBF_SYNDROM__SERR, dram_syndrom);
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derr = FIELD_GET(MLXBF_SYNDROM__DERR, dram_syndrom);
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syndrom = FIELD_GET(MLXBF_SYNDROM__SYN, dram_syndrom);
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if ((is_single_ecc && !serr) || (!is_single_ecc && !derr)) {
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edac_mc_handle_error(ecc_type, mci, error_cnt, 0, 0, 0,
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0, 0, -1, mci->ctl_name, "");
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return;
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}
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dram_additional_info = readl(priv->emi_base + MLXBF_ADD_INFO);
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err_prank = FIELD_GET(MLXBF_ADD_INFO__ERR_PRANK, dram_additional_info);
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ecc_dimm = (err_prank >= 2 && priv->dimm_ranks[0] <= 2) ? 1 : 0;
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edea0 = readl(priv->emi_base + MLXBF_ERR_ADDR_0);
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edea1 = readl(priv->emi_base + MLXBF_ERR_ADDR_1);
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ecc_dimm_addr = ((u64)edea1 << 32) | edea0;
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edac_mc_handle_error(ecc_type, mci, error_cnt,
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PFN_DOWN(ecc_dimm_addr),
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offset_in_page(ecc_dimm_addr),
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syndrom, ecc_dimm, 0, 0, mci->ctl_name, "");
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}
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static void bluefield_edac_check(struct mem_ctl_info *mci)
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{
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struct bluefield_edac_priv *priv = mci->pvt_info;
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u32 ecc_count, single_error_count, double_error_count, ecc_error = 0;
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/*
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* The memory controller might not be initialized by the firmware
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* when there isn't memory, which may lead to bad register readings.
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*/
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if (mci->edac_cap == EDAC_FLAG_NONE)
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return;
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ecc_count = readl(priv->emi_base + MLXBF_ECC_CNT);
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single_error_count = FIELD_GET(MLXBF_ECC_CNT__SERR_CNT, ecc_count);
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double_error_count = FIELD_GET(MLXBF_ECC_CNT__DERR_CNT, ecc_count);
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if (single_error_count) {
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ecc_error |= MLXBF_ECC_ERR__SECC;
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bluefield_gather_report_ecc(mci, single_error_count, 1);
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}
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if (double_error_count) {
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ecc_error |= MLXBF_ECC_ERR__DECC;
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bluefield_gather_report_ecc(mci, double_error_count, 0);
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}
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/* Write to clear reported errors. */
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if (ecc_count)
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writel(ecc_error, priv->emi_base + MLXBF_ECC_ERR);
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}
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/* Initialize the DIMMs information for the given memory controller. */
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static void bluefield_edac_init_dimms(struct mem_ctl_info *mci)
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{
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struct bluefield_edac_priv *priv = mci->pvt_info;
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int mem_ctrl_idx = mci->mc_idx;
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struct dimm_info *dimm;
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u64 smc_info, smc_arg;
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int is_empty = 1, i;
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for (i = 0; i < priv->dimm_per_mc; i++) {
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dimm = mci->dimms[i];
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smc_arg = mem_ctrl_idx << 16 | i;
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smc_info = smc_call1(MLNX_SIP_GET_DIMM_INFO, smc_arg);
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if (!FIELD_GET(MLXBF_DIMM_INFO__SIZE_GB, smc_info)) {
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dimm->mtype = MEM_EMPTY;
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continue;
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}
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is_empty = 0;
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dimm->edac_mode = EDAC_SECDED;
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if (FIELD_GET(MLXBF_DIMM_INFO__IS_NVDIMM, smc_info))
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dimm->mtype = MEM_NVDIMM;
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else if (FIELD_GET(MLXBF_DIMM_INFO__IS_LRDIMM, smc_info))
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dimm->mtype = MEM_LRDDR4;
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else if (FIELD_GET(MLXBF_DIMM_INFO__IS_RDIMM, smc_info))
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dimm->mtype = MEM_RDDR4;
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else
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dimm->mtype = MEM_DDR4;
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dimm->nr_pages =
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FIELD_GET(MLXBF_DIMM_INFO__SIZE_GB, smc_info) *
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(SZ_1G / PAGE_SIZE);
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dimm->grain = MLXBF_EDAC_ERROR_GRAIN;
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/* Mem controller for BlueField only supports x4, x8 and x16 */
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switch (FIELD_GET(MLXBF_DIMM_INFO__PACKAGE_X, smc_info)) {
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case 4:
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dimm->dtype = DEV_X4;
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break;
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case 8:
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dimm->dtype = DEV_X8;
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break;
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case 16:
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dimm->dtype = DEV_X16;
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break;
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default:
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dimm->dtype = DEV_UNKNOWN;
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}
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priv->dimm_ranks[i] =
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FIELD_GET(MLXBF_DIMM_INFO__RANKS, smc_info);
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}
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if (is_empty)
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mci->edac_cap = EDAC_FLAG_NONE;
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else
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mci->edac_cap = EDAC_FLAG_SECDED;
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}
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static int bluefield_edac_mc_probe(struct platform_device *pdev)
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{
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struct bluefield_edac_priv *priv;
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struct device *dev = &pdev->dev;
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struct edac_mc_layer layers[1];
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struct mem_ctl_info *mci;
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struct resource *emi_res;
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unsigned int mc_idx, dimm_count;
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int rc, ret;
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/* Read the MSS (Memory SubSystem) index from ACPI table. */
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if (device_property_read_u32(dev, "mss_number", &mc_idx)) {
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dev_warn(dev, "bf_edac: MSS number unknown\n");
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return -EINVAL;
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}
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/* Read the DIMMs per MC from ACPI table. */
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if (device_property_read_u32(dev, "dimm_per_mc", &dimm_count)) {
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dev_warn(dev, "bf_edac: DIMMs per MC unknown\n");
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return -EINVAL;
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}
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if (dimm_count > MLXBF_EDAC_MAX_DIMM_PER_MC) {
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dev_warn(dev, "bf_edac: DIMMs per MC not valid\n");
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return -EINVAL;
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}
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emi_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!emi_res)
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return -EINVAL;
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layers[0].type = EDAC_MC_LAYER_SLOT;
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layers[0].size = dimm_count;
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layers[0].is_virt_csrow = true;
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mci = edac_mc_alloc(mc_idx, ARRAY_SIZE(layers), layers, sizeof(*priv));
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if (!mci)
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return -ENOMEM;
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priv = mci->pvt_info;
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priv->dimm_per_mc = dimm_count;
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priv->emi_base = devm_ioremap_resource(dev, emi_res);
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if (IS_ERR(priv->emi_base)) {
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dev_err(dev, "failed to map EMI IO resource\n");
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ret = PTR_ERR(priv->emi_base);
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goto err;
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}
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mci->pdev = dev;
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mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_RDDR4 |
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MEM_FLAG_LRDDR4 | MEM_FLAG_NVDIMM;
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mci->edac_ctl_cap = EDAC_FLAG_SECDED;
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mci->mod_name = DRIVER_NAME;
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mci->ctl_name = "BlueField_Memory_Controller";
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mci->dev_name = dev_name(dev);
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mci->edac_check = bluefield_edac_check;
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/* Initialize mci with the actual populated DIMM information. */
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bluefield_edac_init_dimms(mci);
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platform_set_drvdata(pdev, mci);
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/* Register with EDAC core */
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rc = edac_mc_add_mc(mci);
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if (rc) {
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dev_err(dev, "failed to register with EDAC core\n");
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ret = rc;
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goto err;
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}
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/* Only POLL mode supported so far. */
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edac_op_state = EDAC_OPSTATE_POLL;
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return 0;
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err:
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edac_mc_free(mci);
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return ret;
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}
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static int bluefield_edac_mc_remove(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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edac_mc_del_mc(&pdev->dev);
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edac_mc_free(mci);
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return 0;
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}
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static const struct acpi_device_id bluefield_mc_acpi_ids[] = {
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{"MLNXBF08", 0},
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{}
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};
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MODULE_DEVICE_TABLE(acpi, bluefield_mc_acpi_ids);
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static struct platform_driver bluefield_edac_mc_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.acpi_match_table = bluefield_mc_acpi_ids,
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},
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.probe = bluefield_edac_mc_probe,
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.remove = bluefield_edac_mc_remove,
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};
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module_platform_driver(bluefield_edac_mc_driver);
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MODULE_DESCRIPTION("Mellanox BlueField memory edac driver");
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MODULE_AUTHOR("Mellanox Technologies");
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MODULE_LICENSE("GPL v2");
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